2011 6th IEEE International Symposium on Industrial and Embedded Systems最新文献

Message from the conference chairs 来自会议主席的信息

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-09-11 DOI: 10.1109/ASAP.2011.6043224

M. Ercegovac, E. Swartzlander, Joseph R. Cavallaro, P. Ienne, A. Tenca

引用次数: 1

An IDE for component-based design of embedded real-time software 基于组件的嵌入式实时软件设计IDE

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953677

J. Wiklander, Johan Eriksson, P. Lindgren

引用次数: 1

An engineering approach to synchronization based on overrun for compositional real-time systems 组合实时系统中基于超限同步的工程方法

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953671

U. Keskin, M. V. D. Heuvel, R. J. Bril, J. Lukkien, M. Behnam, Thomas Nolte

{"title":"An engineering approach to synchronization based on overrun for compositional real-time systems","authors":"U. Keskin, M. V. D. Heuvel, R. J. Bril, J. Lukkien, M. Behnam, Thomas Nolte","doi":"10.1109/SIES.2011.5953671","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953671","url":null,"abstract":"Hierarchical scheduling frameworks (HSFs) provide means for composing complex real-time systems from well-defined independently developed and analyzed subsystems. To support shared logical resources requiring mutual exclusive access in two-level HSFs, overrun without payback has been proposed as a mechanism to prevent budget depletion during resource access arbitrated by the stack resource policy (SRP). In this paper, we revisit the global schedulability analysis of synchronization protocols based on SRP and overrun without payback for fixed-priority scheduled HSFs. We derive a new global schedulability analysis based on the observation that the overrun budget is merely meant to prevent budget depletion during global resource access. The deadline of a subsystem therefore only needs to hold for its normal budget rather than the sum of the normal and overrun budget. Our novel analysis is considerably simpler than an earlier, initially improved analysis, which improved both the original local and global schedulability analyses. We evaluate the new analysis based on an extensive simulation study and compare the results with the existing analysis. Our simplified analysis does not significantly affect schedulability compared to the initially improved analysis. It is therefore proposed as a preferable engineering approach to synchronization protocols for compositional real-time systems. We accordingly present the implementation of our improvement in an OSEK-compliant real-time operating system to sketch its applicability in today's industrial automotive standards. Both implementation and run-time overheads are discussed providing measured results1.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124312619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Assessment of trace-differences in timing analysis for Complex Real-Time Embedded Systems 复杂实时嵌入式系统时序分析中的迹差评估

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953672

Yue Lu, Thomas Nolte, I. Bate, J. Kraft, C. Norström

{"title":"Assessment of trace-differences in timing analysis for Complex Real-Time Embedded Systems","authors":"Yue Lu, Thomas Nolte, I. Bate, J. Kraft, C. Norström","doi":"10.1109/SIES.2011.5953672","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953672","url":null,"abstract":"In this paper, we look at identifying temporal differences between different versions of Complex Real-Time Embedded Systems (CRTES) by using timing traces representing response times and execution times of tasks. In particular, we are interested in being able to reason about whether a particular change to CRTES will impact on their temporal performance, which is difficult to answer due to the complicated timing behavior such CRTES have. To be specific, we first propose a sampling mechanism to eliminate dependencies existing in tasks' response time and execution time data in the traces taken from CRTES, which makes any statistical inference in probability theory and statistics realistic. Next, we use a mature statistical method, i.e., the non-parametric two-sample Kolmogorov-Smirnov test, to assess the possible temporal differences between different versions of CRTES by using timing traces. Moreover, we introduce a method of reducing the number of samples used in the analysis, while keeping the accuracy of analysis results. This is not trivial, as collecting a large amount of samples in terms of executing real systems is often costly. Our evaluation using simulation models describing an industrial robotic control system with complicated tasks' timing behavior, indicates that the proposed method can successfully identify temporal differences between different versions of CRTES, if there is any. Furthermore, our proposed method outperforms the other statistical methods, e.g., bootstrap and permutation tests, that are often widely used in contexts, in terms of bearing on the accuracy of results when other methods have failed.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125622681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Let's get less optimistic in measurement-based timing analysis 让我们在基于测量的时序分析中变得不那么乐观

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953663

S. Bünte, Michael Zolda, R. Kirner

引用次数: 14

Robustness in dynamical and control systems 动态与控制系统的鲁棒性

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953661

R. Wisniewski

引用次数: 0

A methodology for designing energy-aware secure embedded systems 一种节能安全嵌入式系统的设计方法

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953687

Mehrdad Saadatmand, A. Cicchetti, Mikael Sjödin

引用次数: 3

State Design Pattern Implementation of a DSP processor: A case study of TMS5416C DSP处理器状态设计模式的实现:以TMS5416C为例

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953682

Tanin Afacan

引用次数: 11

HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs HW-SW实现fpga中基于arm的Cortex-M1 soc的解耦FPU

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953649

Jaume Joven, Per Strict, David Castells-Rufas, Akash Bagdia, G. Micheli, J. Carrabina

{"title":"HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs","authors":"Jaume Joven, Per Strict, David Castells-Rufas, Akash Bagdia, G. Micheli, J. Carrabina","doi":"10.1109/SIES.2011.5953649","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953649","url":null,"abstract":"Nowadays industrial monoprocessor and multiprocessor systems make use of hardware floating-point units (FPUs) to provide software acceleration and better precision due to the necessity to compute complex software applications. This paper presents the design of an IEEE-754 compliant FPU, targeted to be used with ARM Cortex-M1 processor on FPGA SoCs. We face the design of an AMBA-based decoupled FPU in order to avoid changing of the Cortex-M1 ARMv6-M architecture and the ARM compiler, but as well to eventually share it among different processors in our Cortex-M1 MPSoC design. Our HW-SW implementation can be easily integrated to enable hardware-assisted floating-point operations transparently from the software application. This work reports synthesis results of our Cortex-M1 SoC architecture, as well as our FPU in Altera and Xilinx FPGAs, which exhibit competitive numbers compared to the equivalent Xilinx FPU IP core. Additionally, single and double precision tests have been performed under different scenarios showing best case speedups between 8.8× and 53.2× depending on the FP operation when are compared to FP software emulation libraries.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"715 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133085090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Exploring alternatives to scale FTT-SE to large networks 探索将FTT-SE扩展到大型网络的替代方案

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953692

Farahnaz Yekeh, M. Pordel, L. Almeida, M. Behnam, P. Portugal

引用次数: 11