{"title":"A compositional implementation of Modbus in Protege","authors":"Yan Wang, Verónica Gaspes","doi":"10.1109/SIES.2011.5953654","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953654","url":null,"abstract":"Network protocols today play a major role in embedded software for industrial automation, with constant efforts to adapt existing device software to new emerging standards. In earlier work, we have proposed a compilation-based approach using a domain-specific language, Protege, which automatically generates protocol stack implementations in C from modular high-level descriptions. In this paper, we provide a case study of the Protege language in an industrial setting. We have implemented the Modbus protocol over TCP/IP and over serial line, and tested it using an industrial gateway. Our implementation demonstrates Protege's advantages for software productivity, easy maintenance and code reuse, and it achieves many desirable properties of industrial embedded network software.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114515871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Behnam, Farhang Nemati, Thomas Nolte, Håkan Grahn
{"title":"Towards an efficient approach for resource sharing in real-time multiprocessor systems","authors":"M. Behnam, Farhang Nemati, Thomas Nolte, Håkan Grahn","doi":"10.1109/SIES.2011.5953690","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953690","url":null,"abstract":"Supporting resource sharing in multiprocessor architectures is one of the major problems that limit the potential performance benefits of using such architectures for real-time systems. Many approaches and algorithms have been proposed to support resource sharing, however, most of them impose either high blocking times on tasks or require a large memory allocation. In this paper we investigate the possibility of combining the lock-based approaches and wait-free approaches (using multiple buffers) in order to decrease both the blocking times that may affect the schedulability of tasks and the required memory. To achieve this, we propose a solution based on evaluating the maximum allowed blocking time on each task according to the schedulability analysis, and then find the minimum memory allocation for each resource that limits the blocking times on tasks to be less than the maximum allowed blocking times.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131034119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A statistical response-time analysis of complex real-time embedded systems by using timing traces","authors":"Yue Lu, T. Nolte, I. Bate, L. Cucu-Grosjean","doi":"10.1109/SIES.2011.5953676","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953676","url":null,"abstract":"Real-time embedded systems are becoming ever more complex, and we are reaching the stage where even if static Response-Time Analysis (RTA) was feasible from a cost and technical perspective, the results are overly pessimistic making them less useful to the practitioner. When combined with the fact that most timing analysis tends to be statistical in nature, this suggests there should be a move toward statistical RTA. However, to make such analysis useful, it is imperative that we have evidence that the statistical RTA and the information analyzed is sufficiently accurate. In this paper we present and validate a technique for statistical RTA that can cope with systems that are complex from both a size and tasks' dependencies perspective. This claim is backed up by our evaluation using information from real industrial control systems.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116336815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Bloem, K. Chatterjee, Karin Greimel, T. Henzinger, Barbara Jobstmann
{"title":"Specification-centered robustness","authors":"R. Bloem, K. Chatterjee, Karin Greimel, T. Henzinger, Barbara Jobstmann","doi":"10.1109/SIES.2011.5953660","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953660","url":null,"abstract":"In addition to being correct, a system should be robust, that is, it should behave reasonably even after receiving unexpected inputs. In this paper, we summarize two formal notions of robustness that we have introduced previously for reactive systems. One of the notions is based on assigning costs for failures on a user-provided notion of incorrect transitions in a specification. Here, we define a system to be robust if a finite number of incorrect inputs does not lead to an infinite number of incorrect outputs. We also give a more refined notion of robustness that aims to minimize the ratio of output failures to input failures. The second notion is aimed at liveness. In contrast to the previous notion, it has no concept of recovery from an error. Instead, it compares the ratio of the number of liveness constraints that the system violates to the number of liveness constraints that the environment violates.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127336411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Scott Cotton, O. Maler, Julien Legriel, Selma Saidi
{"title":"Multi-criteria optimization for mapping programs to multi-processors","authors":"Scott Cotton, O. Maler, Julien Legriel, Selma Saidi","doi":"10.1109/SIES.2011.5953650","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953650","url":null,"abstract":"Finding tradeoffs in design space is naturally formulated as a multicriteria optimization problem. In this paper, we model tradeoffs between communication cost and the balance of processor workloads for the problem of mapping applications to processors in a multicore environment. We formulate several query strategies for finding Pareto optimal and approximately Pareto optimal solutions to the mapping problem using a constraint solver as a time-bounded oracle. Each of the strategies directs the oracle through the search space in a different manner. We evaluate the efficiency of these strategies on a series of synthetic benchmarks, and on two industrial applications, a video noise reduction, and an image demosaic color filtering. The results indicate a significant tradeoff between precision and computation time, and a corresponding benefit to time-bounded queries.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123907370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Plant control over QoS-enabled packet networks","authors":"D. Quaglia, R. Muradore, P. Fiorini","doi":"10.1109/SIES.2011.5953655","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953655","url":null,"abstract":"Performance and stability in networked control systems are strongly affected by transmission delays and packet dropouts. We propose a control architecture based on the Differentiated Services technique to guarantee quality of service on the network. The crucial observation is that not all signals traveling on the network have the same importance. An adaptive packet-marking strategy has been developed to choose at run-time the transmission priority according to the importance of the data and the current network condition. System/network co-simulation applied to a bottleneck scenario validates the proposed approach and shows that better performance can be reached without increasing the bandwidth if network resources are used in a smarter way.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127726741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Matthias Büker, W. Damm, Günter Ehmen, Alexander Metzner, Ingo Stierand, E. Thaden
{"title":"Automating the design flow for distributed embedded automotive applications: Keeping your time promises, and optimizing costs, too","authors":"Matthias Büker, W. Damm, Günter Ehmen, Alexander Metzner, Ingo Stierand, E. Thaden","doi":"10.1109/SIES.2011.5953658","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953658","url":null,"abstract":"We address the complete design flow from specification models of new automotive functions captured in Matlab-Simulink to their distributed execution on hierarchical bus-based electronic architectures hosting the release of already deployed automotive functions. We propose an automated design space exploration process resulting in a cost-optimized extension of the existing target hardware and an allocation of balanced task structures automatically derived from the specification model on this modified target hardware which is sufficient to guarantee both system-level timing requirements and deadlines extracted from the Matlab-Simulink specification model.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115177844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
David Szczesny, S. Traboulsi, Felix Bruns, S. Hessel, A. Bilgic
{"title":"Exploration of energy efficient acceleration concepts for the ROHCv2 in LTE handsets","authors":"David Szczesny, S. Traboulsi, Felix Bruns, S. Hessel, A. Bilgic","doi":"10.1109/SIES.2011.5953666","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953666","url":null,"abstract":"In this paper, we present different acceleration concepts for the Robust Header Compression version 2 (ROHCv2) algorithms in Long Term Evolution (LTE) handsets. First, we explore the potential performance improvements and energy savings by adopting scratchpad memories at various sizes. Second, dedicated hardware accelerators with different data transfer modes are compared in terms of processing speed and energy efficiency on system level. By applying a virtual prototyping methodology with a proprietary filter module, we are able to investigate these two approaches within a state-of-the-art ARM based mobile phone platform at real software loads. Additionally, combined measurements of the execution time together with an estimation of the energy, that is consumed in the memory and the bus architecture, are performed. With reasonably dimensioned scratchpad memories (16 kB for instructions and data respectively), maximum speedups and energy savings both of approximately 60 % are achieved depending on the cache sizes in the embedded processor. Even better performance, especially in combination with big caches, is reached with a dedicated ROHCv2 hardware accelerator supporting the processing of several packets at once in a so called list mode. Compared to the pure software case, the execution time and the energy consumption are both improved by up to 80 % at small caches and still amount to more than 40 % and almost 30 % at big caches, respectively.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131853696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thread-level speculation as an optimization technique in Web Applications — Initial results","authors":"Jan Kasper Martinsen, Håkan Grahn","doi":"10.1109/SIES.2011.5953686","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953686","url":null,"abstract":"Web Applications have become increasingly popular as they allow developers to use an uniform platform for user interactions. The dynamic programming language JavaScript used in most Web Applications has performance penalties, that have been addressed by traditional optimization techniques. We have found that while the performance gain of such techniques are positive for a set of established benchmarks, it often fails to improve the performance of real-life Web Applications. We suggest Thread-Level Speculation (TLS) at the JavaScript function level to automatically extract parallelism to gain performance. There have been multiple TLS proposals in both hardware and software, but little work has been done within JavaScript. Currently we are implementing our TLS ideas in a state-of-the-art JavaScript engine targeted for embedded mobile devices.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128286759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mechanisms for guaranteeing data consistency and flow preservation in AUTOSAR software on multi-core platforms","authors":"Haibo Zeng, M. Natale","doi":"10.1109/SIES.2011.5953656","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953656","url":null,"abstract":"The implementation of AUTOSAR runnables as a set of concurrent tasks requires the protection of shared communication and state variables implementing interface and internal ports. In addition, in a model-based design flow, the results of the model validation and verification are retained only if the code implementation preserves the semantic properties of interest. Since AUTOSAR does not support the modeling of the internal behavior of runnables, the most likely candidate for the development of the functions behavior is Simulink, which is based on a Synchronous Reactive semantics. Commercial code generation tools offer solutions for preserving the signal flows exchanged among model blocks allocated to the same core, but do not scale to multicore systems. In this paper, we summarize the possible options for the implementation of communication mechanisms that preserve signal flows, and discuss the tradeoff in the implementation of AUTOSAR models on multicore platforms.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130953372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}