Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications最新文献

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Implementation and evaluation of a parallel PMS simulator 并行PMS模拟器的实现与评价
Manohar Rao, Z. Segall
{"title":"Implementation and evaluation of a parallel PMS simulator","authors":"Manohar Rao, Z. Segall","doi":"10.1109/PARBSE.1990.77166","DOIUrl":"https://doi.org/10.1109/PARBSE.1990.77166","url":null,"abstract":"The sources of parallelism in an event-driven simulator have been investigated. First, a simple and straightforward parallelization strategy was implemented. It was observed that this strategy did not provide sufficient parallelism. Then the advance scheduling strategy was developed, which has yielded a significantly higher degree of parallelism. The main contribution of this research has been the development of this advance scheduling strategy. This strategy trades a small amount of inaccuracy in the simulation results for a large gain in the amount of parallelism extracted from the simulator. This strategy can be effectively applied for statistical simulators, because the statistical methods of simulation themselves introduce variations in the results. It was observed that, with a proper choice for the overlap distance, the error in the final results is comparable to the variation in the results introduced by the statistical simulation methods employed. A modified implementation of the event queue (Runqueue), which exploits the disorder in event scheduling created by the advance scheduling strategy, is presented. This implementation should significantly reduce contention for the Runqueue. A simulation model was implemented to simulate a distributed memory architecture proposed by D. Black, Z. Segall, and L. Rudolph. With the help of this simulation model, extensive experiments can be conducted to determine the strengths and weaknesses of the proposed architecture.<<ETX>>","PeriodicalId":389644,"journal":{"name":"Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131859059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A data flow architecture for parallel computation 一种用于并行计算的数据流架构
P. Abellard, G. Nolibe, N. Razafindrakoto
{"title":"A data flow architecture for parallel computation","authors":"P. Abellard, G. Nolibe, N. Razafindrakoto","doi":"10.1109/PARBSE.1990.77130","DOIUrl":"https://doi.org/10.1109/PARBSE.1990.77130","url":null,"abstract":"A qualitative description and a mathematical definition of the data-flow Petri-net model are presented. The data-flow Petri nets are used for the data-flow multiprocessor operation. They can advantageously replace flow graphs for validation, simulation, and scheduling. In the functional assembler language used, the source program describes the function to be processed and does not specify all the steps as do classical assemblers. An application for the control of a telemanipulator robot with image processing is given.<<ETX>>","PeriodicalId":389644,"journal":{"name":"Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122965209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The multibackend database system (MDBS): a performance study 多后端数据库系统(mdb):性能研究
J. Hall, D. K. Hsiao, M. Kamel
{"title":"The multibackend database system (MDBS): a performance study","authors":"J. Hall, D. K. Hsiao, M. Kamel","doi":"10.1109/PARBSE.1990.77133","DOIUrl":"https://doi.org/10.1109/PARBSE.1990.77133","url":null,"abstract":"The authors describe a performance evaluation study of an experimental database computer with a variable number of parallel database backends. They first discuss the performance measures employed for this type of database computer. Next, they describe the benchmarks and interpret the results. Preliminary test results indicate the viability and promise of this type of parallel database computer in performance gain and capacity growth. During the overhead-intensive portion of the performance evaluation, MDBS demonstrated good levels of response-time reduction and response-time invariance.<<ETX>>","PeriodicalId":389644,"journal":{"name":"Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115188597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An accelerating processor for relational operations 用于关系运算的加速处理器
H. Takeda, T. Satoh
{"title":"An accelerating processor for relational operations","authors":"H. Takeda, T. Satoh","doi":"10.1109/PARBSE.1990.77224","DOIUrl":"https://doi.org/10.1109/PARBSE.1990.77224","url":null,"abstract":"A description is given of ROP (relational operations accelerating processor), a component of the relational database processor RINDA. ROP accelerates relational operations, such as sorts and joins, with specialized hardware and pipeline processing. The architecture and the processing algorithm of ROP, as well as its performance evaluations, are described.<<ETX>>","PeriodicalId":389644,"journal":{"name":"Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115448969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parallel function invocation in a dynamic argument-fetching dataflow architecture 动态参数获取数据流架构中的并行函数调用
G. Gao, H. Hum, Y. Wong
{"title":"Parallel function invocation in a dynamic argument-fetching dataflow architecture","authors":"G. Gao, H. Hum, Y. Wong","doi":"10.1109/PARBSE.1990.77126","DOIUrl":"https://doi.org/10.1109/PARBSE.1990.77126","url":null,"abstract":"The basic structure of a dynamic data-flow architecture based on the argument-fetching data-flow principle is outlined. In particular, the authors present a scheme to exploit fine-grain parallelism in function invocation based on the argument-fetching principle. They extend the static architecture by associating a frame of consecutive memory space for each parallel function invocation, called a function overlay, and identify each invocation instance with the base address of its overlay. The scheme gains efficiency by making effective use of the power provided by the argument-fetching data-flow principle: the separation of the instruction scheduling mechanism and the instruction execution. To handle function applications and memory management, the proposed architecture will have a memory overlay manager that is separate from the pipelined execution unit. To verify the design, a set of standard benchmark programs was mapped onto the new architecture and executed on an experimental general-purpose data-flow architecture simulation testbed.<<ETX>>","PeriodicalId":389644,"journal":{"name":"Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121257528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Performance analysis of a cache-coherent multiprocessor based on hierarchical multiple buses 基于分层多总线的缓存相干多处理器性能分析
Qing Yang
{"title":"Performance analysis of a cache-coherent multiprocessor based on hierarchical multiple buses","authors":"Qing Yang","doi":"10.1109/PARBSE.1990.77149","DOIUrl":"https://doi.org/10.1109/PARBSE.1990.77149","url":null,"abstract":"An approximate performance model for a cache-based multiprocessor system interconnected through hierarchical buses is presented. The model constitutes a tree network of queues that contains both open and closed chains and captures the effects of both bus contention and cache/memory interference on the system performance. The cache coherence protocol used in the system is a simplified version of the write-once protocol. A general memory reference pattern is considered instead of uniform reference assumption. Numerical results obtained from the model show a good agreement with the simulation results. The model can be solved efficiently by using the mean value analysis (MVA) algorithm with little computational cost. It is shown that the proposed model can easily be used to study the sharing behavior of the system on the basis of the application environment.<<ETX>>","PeriodicalId":389644,"journal":{"name":"Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129961995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Dynamic alternation between receiver-initiated and sender-initiated load sharing 接收方发起和发送方发起的负载共享之间的动态交替
A. Svensson
{"title":"Dynamic alternation between receiver-initiated and sender-initiated load sharing","authors":"A. Svensson","doi":"10.1109/PARBSE.1990.77223","DOIUrl":"https://doi.org/10.1109/PARBSE.1990.77223","url":null,"abstract":"The author proposes a new distributed adaptive load-sharing scheme, called Alternate, that alternates between sender and receiver, dynamically depending on the current system load, with the goal of obtaining good performance at all load levels. The system is assumed to be in one of two states depending on whether sender or receiver is currently applied. The state is changed when any node fails in its load-sharing task, that is, when a node using sender does not find a lightly loaded node or a node utilizing receiver fails to find more work. Simulation was used to evaluate sender, receiver, the combined approach, and the alternating approach in a workstation environment. Sender was found to behave better than receiver at light load levels, whereas receiver is superior at higher loads. Alternate's performance is superior or equal to the best attained by sender, receiver, and the combined scheme. Alternate performs best when job interarrival time and resource demands vary greatly.<<ETX>>","PeriodicalId":389644,"journal":{"name":"Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114344213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A parallel processing strategy for computing transitive closure of a database relation 一种计算数据库关系传递闭包的并行处理策略
Keh-Chang Guh
{"title":"A parallel processing strategy for computing transitive closure of a database relation","authors":"Keh-Chang Guh","doi":"10.1109/PARBSE.1990.77115","DOIUrl":"https://doi.org/10.1109/PARBSE.1990.77115","url":null,"abstract":"A strategy for parallel computation of transitive closure of a database relation is given. It uses a hashing technique for horizontal data partitioning to achiev high parallelism with a simple scheme of message passing. A performance analysis shows that the strategy may achieve high parallelism with small communication overhead.<<ETX>>","PeriodicalId":389644,"journal":{"name":"Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126989773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Prolog oriented architecture using RISC concepts 使用RISC概念的面向Prolog的体系结构
Hatim Aboalsamh
{"title":"Prolog oriented architecture using RISC concepts","authors":"Hatim Aboalsamh","doi":"10.1109/PARBSE.1990.77131","DOIUrl":"https://doi.org/10.1109/PARBSE.1990.77131","url":null,"abstract":"It is pointed out that finding the most frequently used machine-level instructions for a particular high-level language (HLL) is one of the design foundations of reduced-instruction-set computers (RISCs). In the present work, the author presents preliminary results of a study to determine the most frequently used machine-level instruction in the execution of Prolog programs. It is noted that three groups (transfer of control, move, and pop/push) must be studied more closely. The transfer of control and the push/pop groups will participate in the design of the overlapping register windows (ORWs) for the anticipated RISC-Prolog machine. The move group will also influence the design of ORWs in terms of the size of the window frames (number of registers per window) and the different replacement strategies of the ORWs.<<ETX>>","PeriodicalId":389644,"journal":{"name":"Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications","volume":"31 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of large memory on the performance of optimistic concurrency control schemes 大内存对乐观并发控制方案性能的影响
Philip S. Yu, D. Dias
{"title":"Impact of large memory on the performance of optimistic concurrency control schemes","authors":"Philip S. Yu, D. Dias","doi":"10.1109/PARBSE.1990.77120","DOIUrl":"https://doi.org/10.1109/PARBSE.1990.77120","url":null,"abstract":"Under optimistic concurrency control (OCC) schemes, the buffer hit ratio and hence the abort probability of a rerun transaction can be affected by its previous runs, since the data items brought in from the previous runs may still be in memory. It is noted that this buffering effect on rerun transactions has been ignored in previous performance studies. In the present work the authors examine its effect on different OCC schemes. It is shown that, with sufficient buffer, a new approach to buffer management can be adopted so that data items referenced by aborted transactions continue to be retained in memory for access during rerun. By considering the I/O reduction during rerun, it is found that, at high contention levels, the broadcast OCC which attempts to abort conflicting transactions as early as possible can be inferior to the pure OCC which only aborts a transaction at its commit time. Second, combining the two schemes, with pure OCC during the first run of a transaction and broadcast OCC during any reruns, can typically lead to better performance, especially at high contention levels.<<ETX>>","PeriodicalId":389644,"journal":{"name":"Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122409783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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