Performance analysis of a cache-coherent multiprocessor based on hierarchical multiple buses

Abstract

An approximate performance model for a cache-based multiprocessor system interconnected through hierarchical buses is presented. The model constitutes a tree network of queues that contains both open and closed chains and captures the effects of both bus contention and cache/memory interference on the system performance. The cache coherence protocol used in the system is a simplified version of the write-once protocol. A general memory reference pattern is considered instead of uniform reference assumption. Numerical results obtained from the model show a good agreement with the simulation results. The model can be solved efficiently by using the mean value analysis (MVA) algorithm with little computational cost. It is shown that the proposed model can easily be used to study the sharing behavior of the system on the basis of the application environment.<>