2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)最新文献

A Low-power Neural 3D Rendering Processor with Bio-inspired Visual Perception Core and Hybrid DNN Acceleration 具有仿生视觉感知核心和混合DNN加速的低功耗神经3D渲染处理器

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2023-04-19 DOI: 10.1109/COOLCHIPS57690.2023.10122036

Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, H. Yoo

引用次数: 0

Keynote and Invited Speakers Biography 主题演讲和特邀演讲者简介

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2023-04-19 DOI: 10.1109/coolchips57690.2023.10122034

引用次数: 0

Lookup Table Modular Reduction: A Low-Latency Modular Reduction for Fast ECC Processor 查找表模块化缩减:用于快速ECC处理器的低延迟模块化缩减

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2023-04-19 DOI: 10.1109/COOLCHIPS57690.2023.10122002

Anawin Opasatian, M. Ikeda

{"title":"Lookup Table Modular Reduction: A Low-Latency Modular Reduction for Fast ECC Processor","authors":"Anawin Opasatian, M. Ikeda","doi":"10.1109/COOLCHIPS57690.2023.10122002","DOIUrl":"https://doi.org/10.1109/COOLCHIPS57690.2023.10122002","url":null,"abstract":"Modular multiplication is used extensively in many cryptosystems, such as in Elliptic Curve Cryptography (ECC). This is why the speed of the modular multiplication has a high impact on the overall speed of the cryptography computation. Recent works utilizing a lookup table for inferring value have shown a promising way for fast computation of modular re-duction, which can be used to construct a much faster modular multiplier than the conventional methods on FPGA. In this work, we explore an alternative way to implement the said technique, which we will call Lookup Table Modular Reduction (LUTMR). We show that in this technique, the modulo value used for generating the modular reduction circuit has a high impact on the generated circuit efficiency. With the LUTMR technique, three modular multipliers for curve Secp256k1, NIST-P384, and BLS12-381 are implemented on FPGA, which has shown to be the fastest compared to recent works. The NIST-P384 ECC processor is also implemented with the designed modular multiplier. It can compute the scalar multiplication in $75.08 mu mathrm{s}$, the fastest and lowest in Time-Area criteria among recent works.","PeriodicalId":387793,"journal":{"name":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129294872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System 三维标准芯片堆叠系统TSV数据流网络的FPGA仿真

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2023-04-19 DOI: 10.1109/COOLCHIPS57690.2023.10122025

Takeshi Ohkawa, M. Aoyagi

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Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance 固态退火处理器灵活可控动态冷却方法提高组合优化性能

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2023-04-19 DOI: 10.1109/COOLCHIPS57690.2023.10121990

Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura

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Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board 基于几何高阶去相关的源分离在FPGA板上的低功耗实现

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2023-04-19 DOI: 10.1109/COOLCHIPS57690.2023.10121954

Ziquan Qin, Kaijie Wei, H. Amano, K. Nakadai

引用次数: 0

A Real-Time Keyword Spotting System Based on an End-To-End Binary Convolutional Neural Network in FPGA 基于端到端二进制卷积神经网络的实时关键字识别系统

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2023-04-19 DOI: 10.1109/COOLCHIPS57690.2023.10121981

Jinsung Yoon, Dong-Hwi Lee, Neungyun Kim, Su-Jung Lee, Gil-Ho Kwak, Tae-Hwan Kim

引用次数: 0

MazeCov-Q: An Efficient Maze-Based Reinforcement Learning Accelerator for Coverage

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2023-04-19 DOI: 10.1109/COOLCHIPS57690.2023.10122120

Infall Syafalni, Mohamad Imam Firdaus, A. M. R. Ilmy, N. Sutisna, T. Adiono

引用次数: 0

A 2.41-μW/MHz, 437-PE/mm2 CGRA in 22 nm FD-SOI With RISC-Like Code Generation 一个2.41 μ w /MHz, 437-PE/mm2的22 nm FD-SOI CGRA与类risc代码生成

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2023-04-19 DOI: 10.1109/COOLCHIPS57690.2023.10121985

Tobias Kaiser, F. Gerfers

{"title":"A 2.41-μW/MHz, 437-PE/mm2 CGRA in 22 nm FD-SOI With RISC-Like Code Generation","authors":"Tobias Kaiser, F. Gerfers","doi":"10.1109/COOLCHIPS57690.2023.10121985","DOIUrl":"https://doi.org/10.1109/COOLCHIPS57690.2023.10121985","url":null,"abstract":"While coarse-grained reconfigurable arrays (CGRAs) have the potential to improve energy efficiency in general-purpose computing beyond the limitations of von Neumann architectures, they suffer from challenges in code generation. Pasithea-l is a CGRA architecture that aims to combine high energy efficiency with RISC-like programmability. This paper presents its first silicon prototype and a C compiler that uses conventional CPU compiler techniques. Compared to code generation for traditional CGRAs, which require expensive place and route steps, this method of code generation reduces compile times and compiler complexity significantly. Performance and power were measured for a set of benchmark programs written in C. On average, energy efficiency of 195.1 int32 MIPS/mW and active power of 2.41μW/MHz were achieved. Peak energy efficiency of 558.2 MIPS/mW and peak performance of 97.5 MIPS were measured. Load/store instructions and instruction transfers are identified as critical factors for energy efficiency in Pasithea. In comparison to an MCU with state-of-the-art energy efficiency, Pasithea achieves higher energy efficiency in four of the benchmarked programs. Switched capacitance per benchmark run was reduced by a factor of approximately 1.4, on average. Its 0.75 mm2 core area and fabric density of 437 Plis/mm2 enable use in cost-sensitive applications and permit further upscaling.","PeriodicalId":387793,"journal":{"name":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114449203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory 缓存:安全非易失性存储器的高性能联合子树完整性验证

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2023-04-19 DOI: 10.1109/COOLCHIPS57690.2023.10122117

Tatsuya Kubo, Shinya Takamaeda-Yamazaki

{"title":"Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory","authors":"Tatsuya Kubo, Shinya Takamaeda-Yamazaki","doi":"10.1109/COOLCHIPS57690.2023.10122117","DOIUrl":"https://doi.org/10.1109/COOLCHIPS57690.2023.10122117","url":null,"abstract":"Data confidentiality, integrity, and persistence are essential in secure non-volatile memory (NVM) systems. However, the cost of persisting all affected security metadata is high and leads to non-negligible overheads, including performance degradation, memory lifetime reduction, and high energy consumption. This is because integrity trees, which are typically used for data authentication of NVMs, require additional cryptographic calculations and memory accesses to persist the metadata for the recovery. In this paper, we propose Cachet, a novel integrity verification scheme that leverages set hash functions to achieve high performance and crash consistency. Specifically, Cachet maintains two set hash values representing the metadata cache state to enable the lazy update of the integrity tree in a joint-subtree manner with minimal overheads. The observation that underlies Cachet is that regarding the metadata cache, the integrity of each cached node is never verified individually, and the recovery process requires just the digest of the cached metadata. Our evaluation results show that Cachet reduces the application execution time by 21%, NVM writes by 30%, and hash calculations by 36% compared to the state-of-art solutions.","PeriodicalId":387793,"journal":{"name":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125552997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0