Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, H. Yoo
{"title":"A Low-power Neural 3D Rendering Processor with Bio-inspired Visual Perception Core and Hybrid DNN Acceleration","authors":"Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, H. Yoo","doi":"10.1109/COOLCHIPS57690.2023.10122036","DOIUrl":null,"url":null,"abstract":"This paper presents a low-power neural 3D rendering processor which can support both inference (INF) and training of the deep neural network (DNN). The processor is realized with four key features: 1) bio-inspired visual perception core (VPC), 2) neural engines using hybrid sparsity exploitation, 3) dynamic neural network allocation (DNNA) core with centrifugal-sampling (CS), and 4) hierarchical weight memory (HWM) with input-channel (iCh) pre-fetcher. Thanks to the VPC and the proposed DNN acceleration architecture, it can improve throughput by 4174x and demonstrates> 30 FPS rendering while consuming 133 mW power.","PeriodicalId":387793,"journal":{"name":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COOLCHIPS57690.2023.10122036","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a low-power neural 3D rendering processor which can support both inference (INF) and training of the deep neural network (DNN). The processor is realized with four key features: 1) bio-inspired visual perception core (VPC), 2) neural engines using hybrid sparsity exploitation, 3) dynamic neural network allocation (DNNA) core with centrifugal-sampling (CS), and 4) hierarchical weight memory (HWM) with input-channel (iCh) pre-fetcher. Thanks to the VPC and the proposed DNN acceleration architecture, it can improve throughput by 4174x and demonstrates> 30 FPS rendering while consuming 133 mW power.