2012 13th International Workshop on Cellular Nanoscale Networks and their Applications最新文献

Automatic generation of locally controlled arithmetic unit via floorplan based partitioning 通过基于平面图的分区自动生成本地控制的算术单元

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Pub Date : 2012-10-18 DOI: 10.1109/CNNA.2012.6331442

C. Nemes, Z. Nagy, P. Szolgay

{"title":"Automatic generation of locally controlled arithmetic unit via floorplan based partitioning","authors":"C. Nemes, Z. Nagy, P. Szolgay","doi":"10.1109/CNNA.2012.6331442","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331442","url":null,"abstract":"In the paper a framework for generating a locally controlled arithmetic unit is presented including graph generation from a mathematical expression, graph partitioning to determine locally controlled parts of the design and VHDL generation. The output of the framework is a pipelined architecture containing locally controlled groups of floating point units. It is demonstrated that both partitioning and placement aspects of the design have to be considered to obtain a highspeed circuit. In a well-placeable design locally controlled groups can be mapped to FPGA in such a way that only neighboring groups communicate with each other. In the presented algorithm an initial floorplan of the floating point units is produced and a novel graph partitioning representation is used for partitioning the floating point units to obtain a well-placeable design. The framework is demonstrated during the automatic circuit generation of a complex mathematical expression related to Computation Fluid Dynamics (CFD). The framework produces 15-27% faster design than the unpartitioned, globally controlled one in the price of a modest area increase. The framework automatically produces well-placeable deadlock-free partitions for complex expressions as well, while in case of traditional partitioners these objectives cannot be targeted.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123712528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Cellular Neural Networks with dynamic cell activity control for Hausdorff distance estimation 基于动态细胞活动控制的细胞神经网络用于Hausdorff距离估计

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Pub Date : 2012-10-18 DOI: 10.1109/CNNA.2012.6331415

M. Janczyk, K. Slot

引用次数: 0

Examining the accuracy and the precision of PDEs for FPGA computations 在FPGA计算中检验偏微分方程的精度和精度

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Pub Date : 2012-10-18 DOI: 10.1109/CNNA.2012.6331439

A. Kiss, Z. Nagy, Á. Csík, P. Szolgay

引用次数: 1

Advanced memristive model of synapses with adaptive thresholds 具有自适应阈值的突触的高级记忆模型

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Pub Date : 2012-10-18 DOI: 10.1109/CNNA.2012.6331459

Weiran Cai, Ronald Tetzlaff

引用次数: 9

FPGA-based generation of autowaves in Memristive Cellular Neural Networks 记忆细胞神经网络中基于fpga的自动波生成

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Pub Date : 2012-10-18 DOI: 10.1109/CNNA.2012.6331435

V. Pham, A. Buscarino, M. Frasca, L. Fortuna, T. Hoang

引用次数: 1

MRL — Memristor Ratioed Logic MRL -忆阻器比率逻辑

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Pub Date : 2012-10-18 DOI: 10.1109/CNNA.2012.6331426

Shahar Kvatinsky, Nimrod Wald, Guy Satat, A. Kolodny, U. Weiser, E. Friedman

引用次数: 230

Non-Boolean associative architectures based on nano-oscillators 基于纳米振荡器的非布尔关联体系结构

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Pub Date : 2012-10-18 DOI: 10.1109/CNNA.2012.6331473

S. Levitan, Yan Fang, D. Dash, T. Shibata, D. Nikonov, G. Bourianoff

引用次数: 53

Study on application of Reference Conjugated Hologram for aberration correction of multiple object planes 参考共轭全息图在多物面像差校正中的应用研究

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Pub Date : 2012-10-18 DOI: 10.1109/CNNA.2012.6331445

B. Nagy, S. Tõkés

引用次数: 0

An Associative Memory with oscillatory CNN arrays using spin torque oscillator cells and spin-wave interactions architecture and End-to-end Simulator 基于自旋力矩振荡器单元、自旋波相互作用结构和端到端模拟器的振荡CNN阵列联想存储器

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Pub Date : 2012-10-18 DOI: 10.1109/CNNA.2012.6331463

T. Roska, A. Horváth, A. Stubendek, F. Corinto, G. Csaba, W. Porod, T. Shibata, G. Bourianoff

引用次数: 18

Real-time use of GPUs in NA62 experiment gpu在NA62实验中的实时使用

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Pub Date : 2012-10-18 DOI: 10.1109/CNNA.2012.6331454

G. Collazuol, V. Innocente, G. Lamanna, F. Pantaleo, M. Sozzi

{"title":"Real-time use of GPUs in NA62 experiment","authors":"G. Collazuol, V. Innocente, G. Lamanna, F. Pantaleo, M. Sozzi","doi":"10.1109/CNNA.2012.6331454","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331454","url":null,"abstract":"We describe a pilot project for the use of GPUs in a real-time triggering application in the early trigger stages at the CERN NA62 experiment, and the results of the first field tests together with a prototype data acquisition (DAQ) system. This pilot project within NA62 aims at integrating GPUs into the central L0 trigger processor, and also to use them as fast online processors for computing trigger primitives. Several TDC-equipped sub-detectors with sub-nanosecond time resolution will participate in the first-level NA62 trigger (L0), fully integrated with the data-acquisition system, to reduce the readout rate of all sub-detectors to 1 MHz, using multiplicity information asynchronously computed over time frames of a few ns, both for positive sub-detectors and for vetos. The online use of GPUs would allow the computation of more complex trigger primitives already at this first trigger level. We describe the architectures of the proposed systems, focusing on measuring the performance (both throughput and latency) of various approaches meant to solve these high energy physics problems. The challenges and the prospects of this promising idea are discussed.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125555697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6