2006 IEEE Region 5 Conference最新文献_第5页

HVDC transmission to mitigate electric energy crisis in the United States 高压直流输电缓解美国电力危机

2006 IEEE Region 5 Conference Pub Date : 2006-04-07 DOI: 10.1109/TPSD.2006.5507422

K. Meah, S. Ula

引用次数: 0

The good intentions of IEEE standard 1180, may it rest in peace IEEE 1180标准的美好愿望，愿它安息吧

2006 IEEE Region 5 Conference Pub Date : 2006-04-07 DOI: 10.1109/TPSD.2006.5507447

K. Vollmar

引用次数: 0

Fault-tolerant FPGAs by online ECC verification and restoration 通过在线ECC验证和恢复的容错fpga

2006 IEEE Region 5 Conference Pub Date : 2006-04-07 DOI: 10.1109/TPSD.2006.5507454

E. Hjortland, Li Chen

引用次数: 5

Comparison of active filtering with multipulse input current shaping techniques for AC-DC converters 交直流变换器有源滤波与多脉冲输入电流整形技术的比较

2006 IEEE Region 5 Conference Pub Date : 2006-04-07 DOI: 10.1109/TPSD.2006.5507429

M. Peterson, Brij N. Singh

引用次数: 2

A new secure adaptive steganographic algorithm using Fibonacci numbers 一种基于斐波那契数的安全自适应隐写算法

2006 IEEE Region 5 Conference Pub Date : 2006-04-07 DOI: 10.1109/TPSD.2006.5507446

S. Agaian, Ravindranath Cherukuri, Ronnie R. Sifuentes

引用次数: 15

Cut saturation for p-cycle design p循环设计的切割饱和度

2006 IEEE Region 5 Conference Pub Date : 2006-04-07 DOI: 10.1109/TPSD.2006.5507423

Khalid Al-Snaie, D. Thompson

引用次数: 0

Software hazard generation with model checking 软件危险生成与模型检查

2006 IEEE Region 5 Conference Pub Date : 2006-04-07 DOI: 10.1109/TPSD.2006.5507458

Phongphun Kijsanayothin, R. Hewett, Jingsong Wang, Meinhard Peters

引用次数: 0

High performance RF SOI MOSFET varactor modeling and design 高性能RF SOI MOSFET变容器建模与设计

2006 IEEE Region 5 Conference Pub Date : 2006-04-07 DOI: 10.1109/TPSD.2006.5507455

Jianning Wang, Jason Roland, J. Popp, X. Zhu, C. Hutchens, Yumin Zhang

引用次数: 7

Performance of two-stage massive correlator architecture for fast acquisition of GPS signals GPS信号快速采集的两级海量相关器结构性能

2006 IEEE Region 5 Conference Pub Date : 2006-04-07 DOI: 10.1109/TPSD.2006.5507444

D. Akopian, P. Sagiraju, S. Turunen

{"title":"Performance of two-stage massive correlator architecture for fast acquisition of GPS signals","authors":"D. Akopian, P. Sagiraju, S. Turunen","doi":"10.1109/TPSD.2006.5507444","DOIUrl":"https://doi.org/10.1109/TPSD.2006.5507444","url":null,"abstract":"A typical operation of GPS receivers assumes a search of the satellites visible on the sky by synchronizing locally generated replica with the transmitted pseudo-random noise (PRN) code sequence. This synchronization is initially performed by finding the highest correlation between the incoming signal and replica, a process known as “acquisition”. Highest correlation is observed as a correlator peak response which is compared with a certain threshold to identify availability and values of unknown code phase and frequency of a residual carrier modulation. If the peak is not detected or the decision is wrong then acquisition stage should be repeated many times which is quite a time consuming task. State-of-the-art advanced receivers use massive correlators which parallelize the acquisition process. While massive correlators improve significantly the sensitivity of the receivers, so-called multiple peak selection approach provides an opportunity to save computations by sharing tasks between the massive correlator and validation system [1]. In this paper we study a performance of two stage correlator consisting of massive and supplementary implementations. The massive correlator is not making firm decisions each time it finds a peak, but provides several possible options (a limited set of highest peaks) to supplementary system.","PeriodicalId":385396,"journal":{"name":"2006 IEEE Region 5 Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132247314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A one gigaFLIPS fuzzy logic control chip using only combinational logic and Field Programmable Gate Arrays 一种仅使用组合逻辑和现场可编程门阵列的千兆模糊逻辑控制芯片

2006 IEEE Region 5 Conference Pub Date : 2006-04-07 DOI: 10.1109/TPSD.2006.5507464

Lars Terum, Brian Hernmelman

引用次数: 1