{"title":"Secure voice over Internet Protocol (voIP) using virtual private networks (VPN) and Internet Protocol Security (IPSec)","authors":"Sergio Chacón, D. Benhaddou, D. Gurkan","doi":"10.1109/TPSD.2006.5507428","DOIUrl":"https://doi.org/10.1109/TPSD.2006.5507428","url":null,"abstract":"The transmission of voice information over the Internet Protocol (VoIP) offers many security challenges. After identification of the security risks, it becomes clear that most of the vulnerabilities occur in the way that voice information is handled in the IP layer [1]. This study proposes a solution using dedicated VPN-based local area firewalls. These firewalls provide more security than a border router by making the voice information less susceptible to attacks from an insider to the network. Plus, they can easily and reliably handle and protect several types of clients in small office environments, control access restricting traffic coming into the inside network and encrypt IP voice packets using IPSec tunneling before the voice packets reach the access switch.","PeriodicalId":385396,"journal":{"name":"2006 IEEE Region 5 Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127194679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hybrid compensation techniques for direct on line starting of high power induction motor","authors":"M. Peterson, Brij N. Singh","doi":"10.1109/TPSD.2006.5507420","DOIUrl":"https://doi.org/10.1109/TPSD.2006.5507420","url":null,"abstract":"The direct on line (DOL) starting of a high power induction motor causes an acute voltage sag in the power supply system. Line to line and line to ground faults are some of the causes for voltage sags and voltage unbalance in the power supply system for industries and commercial buildings. This paper investigates hybrid compensation techniques to solve power quality problems arising from the DOL starting of a high power induction motor. The proposed solution utilizes the Static Compensator (STATCOM) and Static Synchronous Series Compensator (SSSC). In the proposed solution for voltage sags, STATCOM and SSSC are considered as the system components; therefore, a detailed mathematical model is developed for these components as well as a mathematical formulation of the proposed control schemes. Simulation results for STATCOM and SSSC based compensators are given.","PeriodicalId":385396,"journal":{"name":"2006 IEEE Region 5 Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125966308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Raytheon Enterprise Management System Reference Architecture","authors":"Steve Smith, S. Norton","doi":"10.1109/TPSD.2006.5507467","DOIUrl":"https://doi.org/10.1109/TPSD.2006.5507467","url":null,"abstract":"Raytheon Information Systems is actively involved in numerous Network Centric development programs. A common element for these programs is an Enterprise Management System (EMS) responsible for all facets of network operations. The Raytheon EMS Reference Architecture (REMSRA) provides technical descriptions, COTS implementation options, and cost estimation information that can be directly inserted into engineering proposals. REMSRA consolidates EMS knowledge into a single consistent set of documentation artifacts that can be maintained, re-used, and tailored as appropriate. REMSRA describes 16 functional capabilities generally required by customers. From these functions, three architectures were developed addressing basic, intermediate, and advanced system needs. With these architectures, EMS designers have a starting point for engineering their systems based on customer requirements; REMSRA has been applied to commercial and classified customer programs and proposals.","PeriodicalId":385396,"journal":{"name":"2006 IEEE Region 5 Conference","volume":"484 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115321122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and implementation of a CMOS non-restoring divider","authors":"P. Nair, D. Kudithipudi, E. John","doi":"10.1109/TPSD.2006.5507427","DOIUrl":"https://doi.org/10.1109/TPSD.2006.5507427","url":null,"abstract":"The process of binary division is the most complicated and slow among all the binary arithmetic operation. Although division is an infrequent operation compared to addition and multiplication, its longer latency makes division dissipate a significant amount of energy. This longer latency is due to the introduction of additional condition checking, which is necessary for correct functioning. The energy dissipation of dividers is comparable to that of floating-point adders. In order to achieve high performance with minimum energy dissipation, it is necessary to have efficient division algorithms. This paper presents an implementation of one such algorithm. The proper choice of the divider architecture is therefore essential for achieving low-power dissipation, high design flexibility and high reusability of existing building blocks of digital arithmetic and logic units.","PeriodicalId":385396,"journal":{"name":"2006 IEEE Region 5 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114988774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gayathri Sarivisetti, E. Kougianos, S. Mohanty, Atmaram Palakodety, A. K. Ale
{"title":"Optimization of a 45nm CMOS voltage controlled oscillator using design of experiments","authors":"Gayathri Sarivisetti, E. Kougianos, S. Mohanty, Atmaram Palakodety, A. K. Ale","doi":"10.1109/TPSD.2006.5507456","DOIUrl":"https://doi.org/10.1109/TPSD.2006.5507456","url":null,"abstract":"We present a design of experiments (DOE) approach to nanometer design of an analog voltage controlled oscillator (VCO) using CMOS technology. The functional specifications of the VCO optimized in this design are the center frequency and minimization of overall power consumption as well as minimization of power due to gate tunneling current leakage, a component that was not important in previous generations of CMOS technologies but is dominant at 45nm. Due to the large number of available design parameter (gate oxide thickness and transistor sizes), the concurrent achievement of all optimization goals is difficult. A DOE approach is shown to be very effective and a viable alternative to standard design exploration in the nanometer regime.","PeriodicalId":385396,"journal":{"name":"2006 IEEE Region 5 Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127419140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cryptographic transitions","authors":"R. Poore","doi":"10.1201/9781439833032.ch79","DOIUrl":"https://doi.org/10.1201/9781439833032.ch79","url":null,"abstract":"A cryptographic transition is defined as managing the passage from one security architecture to another in a methodical approach that is consistent with prudent business practices and security guidelines. This paper addresses the three technology issues that drive the business and security justifications for initiating a transition; the principles guiding policy and practices when conducting a transition; the process to conduct a successful transition; and provides the pros and cons of several actual case studies of cryptographic transitions.","PeriodicalId":385396,"journal":{"name":"2006 IEEE Region 5 Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132654221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}