Optimization of a 45nm CMOS voltage controlled oscillator using design of experiments

Abstract

We present a design of experiments (DOE) approach to nanometer design of an analog voltage controlled oscillator (VCO) using CMOS technology. The functional specifications of the VCO optimized in this design are the center frequency and minimization of overall power consumption as well as minimization of power due to gate tunneling current leakage, a component that was not important in previous generations of CMOS technologies but is dominant at 45nm. Due to the large number of available design parameter (gate oxide thickness and transistor sizes), the concurrent achievement of all optimization goals is difficult. A DOE approach is shown to be very effective and a viable alternative to standard design exploration in the nanometer regime.