{"title":"A soft multiuser demodulation for non-binary LDPC coded FFH MA/MFSK systems","authors":"S. Su, Her-Chang Tsai, Ye-Shun Shen","doi":"10.1109/TENCON.2007.4429157","DOIUrl":"https://doi.org/10.1109/TENCON.2007.4429157","url":null,"abstract":"A multiuser detection scheme is proposed for non- binary LDPC coded FFH MA/MFSK system to reduce the bit error rate. To mitigate the soft ambiguity in the multiuser detection, a three-level hard-limiter on each chip is proposed with the detection thresholds determined by maximum-likelihood criterion. Based on the evaluation of PDFs of chip corresponding to different number of users hit on it, soft output is derived. Since the channel is non-binary, non-binary LDPC code make there no binary-symbol conversion loss between multiuser detection and channel decoder. Those users whose soft reliability values of the estimated coded symbols exceed a predefined threshold are defined as reliable users. As iteration proceeds, the number of reliable users is increased and multiuser detection process is carried out. Numerical results show that in both AWGN and Rayleigh fading channels, the performances of three-level systems outperform two-level systems and performances in AWGN channels are better than that in Rayleigh channels. However, for two-level systems, the performance in AWGN channel takes no benefit over Rayleigh channel due to useful information is lost.","PeriodicalId":384583,"journal":{"name":"TENCON 2007 - 2007 IEEE Region 10 Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115800364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chi-Wu Huang, C. Chang, Mao-Yuan Lin, Hung-Yun Tai
{"title":"Compact FPGA implementation of 32-bits AES algorithm using Block RAM","authors":"Chi-Wu Huang, C. Chang, Mao-Yuan Lin, Hung-Yun Tai","doi":"10.1109/TENCON.2007.4429126","DOIUrl":"https://doi.org/10.1109/TENCON.2007.4429126","url":null,"abstract":"Hardware implementation of advanced encryption standard (AES) algorithm has been in intensive discussion since its first publication by National Institute of Standards and Technology (NIST) in 2000, especially in high throughput over 1 Giga bits per second (Gbps). However, the studies of low area, low power and low cost implementations, which usually have throughput less than 1 Gbps and use the datapath less than 32-bit, have been appearing recently in ASIC as well as in FPGA for wireless communication and embedded hardware application. This paper proposes a 32-bit datapath implementation in small Xilinx FPGA Chip (Spartan-3 XC3S200). It uses 148 slice, 11 block RAMs (BRAMs) and achieves the data stream of 647 Mega bits per second ( Mbps) at 287 MHz working frequency. It obtains 3.4 times improvement to the best known similar design in terms of ratio throughput per area (Throughput/Area), and 20% smaller in slice area.","PeriodicalId":384583,"journal":{"name":"TENCON 2007 - 2007 IEEE Region 10 Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114964864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling channel conflict probabilities between IEEE 802.11b and IEEE 802.15.1 networks","authors":"Ling-Jyh Chen, Ting-Kai Huang","doi":"10.1109/TENCON.2007.4428889","DOIUrl":"https://doi.org/10.1109/TENCON.2007.4428889","url":null,"abstract":"With the increasingly deployed wireless local/personal area network (WLAN/WPAN) devices, channel conflict has become very frequent and severe when one WLAN/WPAN technology coexists with other WLAN/WPAN technologies in the same interfering range. In this paper, we study the coexistence issue between the most prevalent WLAN and WPAN technologies, namely the IEEE 802.11b and IEEE 802.15.1 standards. We present analytical models on the non-conflicting channel allocation probabilities, focusing on the coexistence scenarios of one IEEE 802.15.1 network coexisting with one or multiple IEEE 802.11b networks. The results show that channel allocation conflicts does occur more frequently as the number of IEEE 802.11b networks increases. Moreover, the proposed analytical model in this letter is simple and applicable to other wireless technologies, as long as the channel allocation mechanisms are known.","PeriodicalId":384583,"journal":{"name":"TENCON 2007 - 2007 IEEE Region 10 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129946286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"How to create identity of anonymous route","authors":"M. Okamoto, Y. Tanaka","doi":"10.1109/TENCON.2007.4429089","DOIUrl":"https://doi.org/10.1109/TENCON.2007.4429089","url":null,"abstract":"Nowadays, anonymity networks are used in various forms. In particular, P2P networks have come to be used widely, wherein anonymity is becoming an important subject. In this paper, we propose a technique to create a route identity for anonymous route. By the route identity we can determine whether a particular transfer route is the same as the previously employed transfer route on an anonymity network.","PeriodicalId":384583,"journal":{"name":"TENCON 2007 - 2007 IEEE Region 10 Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122925135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chih-Hung Kuo, Chih-Hao Hu, Li-Chuan Chang, W. Kuo
{"title":"Robust video quality control with packet scheduling on link layer of DVB-H system","authors":"Chih-Hung Kuo, Chih-Hao Hu, Li-Chuan Chang, W. Kuo","doi":"10.1109/TENCON.2007.4429052","DOIUrl":"https://doi.org/10.1109/TENCON.2007.4429052","url":null,"abstract":"In this paper, we present a technique to improve video quality over DVB-H system adapting to available transmission rate. The technique is based on the concepts of rate-distortion hint track (RDHT)[1] and dynamic forward error correction (DFEC) [2] on the link layer of DVB-H. Simulations using H.264/AVC video were conducted to evaluate the performance of the proposed method. Experimental results show that the proposed scheme demonstrate a significant improvement on video quality while achieving more power saving for the system.","PeriodicalId":384583,"journal":{"name":"TENCON 2007 - 2007 IEEE Region 10 Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132628420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Emotion detection from male speech in computer games","authors":"T. Rudra, M. Kavakli, D. Tien","doi":"10.1109/TENCON.2007.4428779","DOIUrl":"https://doi.org/10.1109/TENCON.2007.4428779","url":null,"abstract":"This paper presents the experimental results of our method of classifying emotional states of neutral and anger of male voice from artificial pidgin utterances using Support vector machine (SVM). The objective of the paper is to demonstrate that a new genre of languages called Game pidgin language (GPL) that can not only be used to capture real time speech recognition, but can also generate response from the non-player-character. The emotion which is a floating point value can be used to generate the corresponding emotive response from the non-player- character (NPC).","PeriodicalId":384583,"journal":{"name":"TENCON 2007 - 2007 IEEE Region 10 Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128295242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel variable grain logic cell architecture with multifunctionality","authors":"R. Yamaguchi, M. Amagasaki, K. Matsuyama","doi":"10.1109/TENCON.2007.4428818","DOIUrl":"https://doi.org/10.1109/TENCON.2007.4428818","url":null,"abstract":"Reconflgurable logic devices are usually classified on the basis of their basic logic cell architecture as fine-grained or coarse-grained type. The coarse-grained architecture is suitable for byte-level processing. On the other hand, the fine-grained architecture is suitable for bit-level processing. The granularity of each type is fixed; therefore, it is difficult to achieve a balance between the operation speed and area efficiency in applications. To overcome this problem, we proposed a variable grain logic cell (VGLC) architecture that can change the operation granularity depending on each application. The VGLC has various functions to achieve both high flexibility and performance. In this paper, we map benchmark designs on the VGLC and compare with it commercial FPGAs. As a result, we show that the proposed architecture improves to cover a maximum 55% of the implementation area.","PeriodicalId":384583,"journal":{"name":"TENCON 2007 - 2007 IEEE Region 10 Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122086682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low-profile loop-shaped inverted-F wire antenna with dualmode operation","authors":"Minseok Kim, H. Arai","doi":"10.1109/TENCON.2007.4428869","DOIUrl":"https://doi.org/10.1109/TENCON.2007.4428869","url":null,"abstract":"This paper proposes a new design of a dualmode operation antenna. We introduced loop-shaped inverted-F wire antenna using a parasitic element within a feeding element for additional resonance mode that has small and low profiled structure. This paper discusses theoretical dual resonance operation and investigates the characteristics along some dimensional parameters by numerical analyses. The measurement results with the proposed structure will be also presented.","PeriodicalId":384583,"journal":{"name":"TENCON 2007 - 2007 IEEE Region 10 Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128276671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Two-dimensional DOA estimation using L-shaped patch array by light load calibration technique","authors":"J. Yaezawa, H. Arai","doi":"10.1109/TENCON.2007.4428883","DOIUrl":"https://doi.org/10.1109/TENCON.2007.4428883","url":null,"abstract":"The conventional calibration techniques require the heavy computation load using large databases or complex calculation including the feeding point and ground plane to obtain the high accuracy. Moreover, there is little discussion that experimental evaluation of calibration methods for two-dimensional (2D-) DOA (direction-of- arrival) estimation. In this paper, we present a calibration technique to reduce computation load and time with thin databases in 2D-DOA estimation. We show the advantage of proposal technique using five- element L-shaped patch array to reduce calibration error and array elements. The estimation with high accuracy is obtained by proposed technique in 2D-DOA estimation using a few percent of databases of the conventional methods. Numerical simulation and experimental results demonstrate the effectiveness of this technique.","PeriodicalId":384583,"journal":{"name":"TENCON 2007 - 2007 IEEE Region 10 Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122513030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault tolerant error coding and detection using reversible gates","authors":"R. K. James, T. Shahana, K. Jacob, S. Sasi","doi":"10.1109/TENCON.2007.4428776","DOIUrl":"https://doi.org/10.1109/TENCON.2007.4428776","url":null,"abstract":"In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction - double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4times4 reversible gate called 'HCG' for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.","PeriodicalId":384583,"journal":{"name":"TENCON 2007 - 2007 IEEE Region 10 Conference","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116048016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}