A novel variable grain logic cell architecture with multifunctionality

Abstract

Reconflgurable logic devices are usually classified on the basis of their basic logic cell architecture as fine-grained or coarse-grained type. The coarse-grained architecture is suitable for byte-level processing. On the other hand, the fine-grained architecture is suitable for bit-level processing. The granularity of each type is fixed; therefore, it is difficult to achieve a balance between the operation speed and area efficiency in applications. To overcome this problem, we proposed a variable grain logic cell (VGLC) architecture that can change the operation granularity depending on each application. The VGLC has various functions to achieve both high flexibility and performance. In this paper, we map benchmark designs on the VGLC and compare with it commercial FPGAs. As a result, we show that the proposed architecture improves to cover a maximum 55% of the implementation area.