Journal of Low Power Electronics and Applications最新文献_第6页

Self-Parameterized Chaotic Map for Low-Cost Robust Chaos 低成本鲁棒混沌的自参数化混沌映射

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2023-02-13 DOI: 10.3390/jlpea13010018

P. Paul, Anur Dhungel, Maisha Sadia, Md Razuan Hossain, Md. Sakib Hasan

{"title":"Self-Parameterized Chaotic Map for Low-Cost Robust Chaos","authors":"P. Paul, Anur Dhungel, Maisha Sadia, Md Razuan Hossain, Md. Sakib Hasan","doi":"10.3390/jlpea13010018","DOIUrl":"https://doi.org/10.3390/jlpea13010018","url":null,"abstract":"This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. The proposed self-parameterization scheme uses only one existing chaotic map, referred to as the seed map, and a simple transformation block. The effective control parameter of the seed map is treated as an intermediate variable derived from the input and control parameter of the self-parameterized map, under some constraints, to achieve the desired functionality. The widening of the chaotic region after adding self-parameterization is first demonstrated on three ideal map functions: Logistic; Tent; and Sine. A digitized version of the scheme was developed and realized in a field-programmable gate array (FPGA) implementation. An analog version of the proposed scheme was developed with very low transistor-count analog topologies for hardware-constrained integrated circuit (IC) implementation. The chaotic performance of both digital and analog implementations was evaluated with bifurcation plots and four established chaotic entropy metrics: the Lyapunov Exponent; the Correlation Coefficient; the Correlation Dimension; and Approximate Entropy. An application of the proposed scheme was demonstrated in a random number generator design, and the statistical randomness of the generated sequence was verified with the NIST test.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"1 1","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70135762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Exploring Topological Semi-Metals for Interconnects 用于互连的拓扑半金属的探索

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2023-02-09 DOI: 10.3390/jlpea13010016

Satwik Kundu, Rupshali Roy, M. Rahman, S. Upadhyay, R. Topaloglu, S. Mohney, Shengxi Huang, Swaroop Ghosh

{"title":"Exploring Topological Semi-Metals for Interconnects","authors":"Satwik Kundu, Rupshali Roy, M. Rahman, S. Upadhyay, R. Topaloglu, S. Mohney, Shengxi Huang, Swaroop Ghosh","doi":"10.3390/jlpea13010016","DOIUrl":"https://doi.org/10.3390/jlpea13010016","url":null,"abstract":"The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44960754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications 适用于低功率应用的1.1V 25 ppm/°C弛豫振荡器，线灵敏度为0.045%/V

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2023-02-07 DOI: 10.3390/jlpea13010015

Yizhuo Liao, P. K. Chan

{"title":"A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications","authors":"Yizhuo Liao, P. K. Chan","doi":"10.3390/jlpea13010015","DOIUrl":"https://doi.org/10.3390/jlpea13010015","url":null,"abstract":"A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) delay-based comparators compensate for the approximated proportional to absolute temperature (PTAT) delay arising from the leakage currents in the switches. This relaxation oscillator is designed to output a square wave with a frequency of 64 kHz in a duty cycle of 50% at a 1.1 V supply. The simulation results demonstrated that the circuit can generate a square wave, with stable frequency, against temperature and supply variation, while exhibiting low current consumption. For the temperature range from −20 °C to 80 °C at a 1.1 V supply, the oscillator’ output frequency achieved a temperature coefficient (T.C.) of 12.4 ppm/°C in a typical corner in one sample simulation. For a 200-sample Monte Carlo simulation, the obtained T.C. is 25 ppm/°C. Under typical corners and room temperatures, the simulated line sensitivity is 0.045%/V with the supply from 1.1 V to 1.6 V, and the dynamic current consumption is 552 nA. A better figure-of-merit (FoM), which equals 0.129%, is displayed when compared to the representative prior-art works.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43332503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Minimum Active Component Count Design of a PIλDμ Controller and Its Application in a Cardiac Pacemaker System pi - λ dμ控制器最小有效成分数设计及其在心脏起搏器系统中的应用

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2023-02-02 DOI: 10.3390/jlpea13010013

Julia Nako, C. Psychalinos, A. Elwakil

引用次数: 4

Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique 采用改进时钟策略技术的宽带级联和堆叠接收机前端

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2023-02-02 DOI: 10.3390/jlpea13010014

A. Abbasi, F. Nabki

{"title":"Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique","authors":"A. Abbasi, F. Nabki","doi":"10.3390/jlpea13010014","DOIUrl":"https://doi.org/10.3390/jlpea13010014","url":null,"abstract":"A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11<−10 dB and an IIP3 from −7.5 dBm to −10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11<−10 dB, and an IIP3 from −21 dBm to −17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42487204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Energy Autonomous Wireless Sensing Node Working at 5 Lux from a 4 cm2 Solar Cell 能量自主无线传感节点工作在5勒克斯从一个4平方厘米的太阳能电池

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2023-02-01 DOI: 10.3390/jlpea13010012

M. Meli, S. Favre, Benjamin Maij, Stefan Stajić, Manuel Boebel, P. Poole, Martin Schellenberg, C. Kouzinopoulos

{"title":"Energy Autonomous Wireless Sensing Node Working at 5 Lux from a 4 cm2 Solar Cell","authors":"M. Meli, S. Favre, Benjamin Maij, Stefan Stajić, Manuel Boebel, P. Poole, Martin Schellenberg, C. Kouzinopoulos","doi":"10.3390/jlpea13010012","DOIUrl":"https://doi.org/10.3390/jlpea13010012","url":null,"abstract":"Harvesting energy for IoT nodes in places that are permanently poorly lit is important, as many such places exist in buildings and other locations. The need for energy-autonomous devices working in such environments has so far received little attention. This work reports the design and test results of an energy-autonomous sensor node powered solely by solar cells. The system can cold-start and run in low light conditions (in this case 20 lux and below, using white LEDs as light sources). Four solar cells of 1 cm2 each are used, yielding a total active surface of 4 cm2. The system includes a capacitive sensor that acts as a touch detector, a crystal-accurate real-time clock (RTC), and a Cortex-M3-compatible microcontroller integrating a Bluetooth Low Energy radio (BLE) and the necessary stack for communication. A capacitor of 100 μF is used as energy storage. A low-power comparator monitors the level of the energy storage and powers up the system. The combination of the RTC and touch sensor enables the MCU load to be powered up periodically or using an asynchronous user touch activity. First tests have shown that the system can perform the basic work of cold-starting, sensing, and transmitting frames at +0 dBm, at illuminances as low as 5 lux. Harvesting starts earlier, meaning that the potential for full function below 5 lux is present. The system has also been tested with other light sources. The comparator is a test chip developed for energy harvesting. Other elements are off-the-shelf components. The use of commercially available devices, the reduced number of parts, and the absence of complex storage elements enable a small node to be built in the future, for use in constantly or intermittently poorly lit places.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44424939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study of Nitrogen-Doped Carbon Nanotubes for Creation of Piezoelectric Nanogenerator 氮掺杂碳纳米管制备压电纳米发电机的研究

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2023-01-22 DOI: 10.3390/jlpea13010011

M. V. Il’ina, O. I. Soboleva, Soslan A. Khubezov, V. Smirnov, O. I. Il’in

引用次数: 1

A Power-Efficient Neuromorphic Digital Implementation of Neural–Glial Interactions 神经-胶质相互作用的高效神经形态数字实现

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2023-01-18 DOI: 10.3390/jlpea13010010

Angeliki Bicaku, Maria Sapounaki, A. Kakarountas, S. Tasoulis

{"title":"A Power-Efficient Neuromorphic Digital Implementation of Neural–Glial Interactions","authors":"Angeliki Bicaku, Maria Sapounaki, A. Kakarountas, S. Tasoulis","doi":"10.3390/jlpea13010010","DOIUrl":"https://doi.org/10.3390/jlpea13010010","url":null,"abstract":"Throughout the last decades, neuromorphic circuits have incited the interest of scientists, as they are potentially a powerful tool for the treatment of neurological diseases. To this end, it is essential to consider the biological principles of the CNS and develop the appropriate area- and power-efficient circuits. Motivated by studies that outline the indispensable role of astrocytes in the dynamic regulation of synaptic transmission and their active contribution to neural information processing in the CNS, in this work we propose a digital implementation of neuron–astrocyte bidirectional interactions. In order to describe the neuronal dynamics and the astrocytes’ calcium dynamics, a modified version of the original Izhikevich neuron model was combined with a linear approximation of the Postnov functional neural–glial interaction model. For the implementation of the neural–glial computation core, only three pipeline stages and a 10.10 fixed point representation were utilized. Regarding the results obtained from the FPGA implementation and the comparisons to other works, the proposed neural–glial circuit reported significant savings in area requirements (from 22.53% up to 164.20%) along with considerable savings in total power consumption of 28.07% without sacrificing output computation accuracy. Finally, an RMSE analysis was conducted, confirming that this particular implementation produces more accurate results compared to previous studies.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42439351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Acknowledgment to the Reviewers of Journal of Low Power Electronics and Applications in 2022 感谢《低功耗电子与应用学报》2022年审稿人

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2023-01-16 DOI: 10.3390/jlpea13010009

引用次数: 0

Numerical Optimization of a Nonlinear Nonideal Piezoelectric Energy Harvester Using Deep Learning 非线性非理想压电能量采集器的深度学习数值优化

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2023-01-12 DOI: 10.3390/jlpea13010008

Andreas Hegendörfer, P. Steinmann, J. Mergheim

{"title":"Numerical Optimization of a Nonlinear Nonideal Piezoelectric Energy Harvester Using Deep Learning","authors":"Andreas Hegendörfer, P. Steinmann, J. Mergheim","doi":"10.3390/jlpea13010008","DOIUrl":"https://doi.org/10.3390/jlpea13010008","url":null,"abstract":"This contribution addresses the numerical optimization of the harvested energy of a mechanically and electrically nonlinear and nonideal piezoelectric energy harvester (PEH) under triangular shock-like excitation, taking into account a nonlinear stress constraint. In the optimization problem, a bimorph electromechanical structure equipped with the Greinacher circuit or the standard circuit is considered and different electrical and mechanical design variables are introduced. Using a very accurate coupled finite element-electronic circuit simulator method, deep neural network (DNN) training data are generated, allowing for a computationally efficient evaluation of the objective function. Subsequently, a genetic algorithm using the DNNs is applied to find the electrical and mechanical design variables that optimize the harvested energy. It is found that the maximum harvested energy is obtained at the maximum possible mechanical stresses and that the optimum storage capacitor for the Greinacher circuit is much smaller than that for the standard circuit, while the total harvested energy by both configurations is similar.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41516502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0