Journal of Low Power Electronics and Applications最新文献_第10页

Electrical Impedance Tomography for Hand Gesture Recognition for HMI Interaction Applications 用于人机界面交互应用的手势识别电阻抗断层扫描

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2022-07-18 DOI: 10.3390/jlpea12030041

Noelia Vaquero-Gallardo, H. Martínez-García

{"title":"Electrical Impedance Tomography for Hand Gesture Recognition for HMI Interaction Applications","authors":"Noelia Vaquero-Gallardo, H. Martínez-García","doi":"10.3390/jlpea12030041","DOIUrl":"https://doi.org/10.3390/jlpea12030041","url":null,"abstract":"Electrical impedance tomography (EIT) is based on the physical principle of bioimpedance defined as the opposition that biological tissues exhibit to the flow of a rotating alternating electrical current. Consequently, here, we propose studying the characterization and classification of bioimpedance patterns based on EIT by measuring, on the forearm with eight electrodes in a non-invasive way, the potential drops resulting from the execution of six hand gestures. The starting point was the acquisition of bioimpedance patterns studied by means of principal component analysis (PCA), validated through the cross-validation technique, and classified using the k-nearest neighbor (kNN) classification algorithm. As a result, it is concluded that reduction and classification is feasible, with a sensitivity of 0.89 in the worst case, for each of the reduced bioimpedance patterns, leading to the following direct advantage: a reduction in the numbers of electrodes and electronics required. In this work, bioimpedance patterns were investigated for monitoring subjects’ mobility, where, generally, these solutions are based on a sensor system with moving parts that suffer from significant problems of wear, lack of adaptability to the patient, and lack of resolution. Whereas, the proposal implemented in this prototype, based on the so-called electrical impedance tomography, does not have these problems.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47159440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Efficiency of Priority Queue Architectures in FPGA FPGA中优先级队列结构的效率

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2022-07-14 DOI: 10.3390/jlpea12030039

L. Kohútka

引用次数: 2

Analysis and Comparison of Different Approaches to Implementing a Network-Based Parallel Data Processing Algorithm 基于网络的并行数据处理算法的不同实现方法的分析与比较

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2022-07-09 DOI: 10.3390/jlpea12030038

I. Skliarova

引用次数: 0

Deep Learning Approaches to Source Code Analysis for Optimization of Heterogeneous Systems: Recent Results, Challenges and Opportunities 面向异构系统优化的源代码分析的深度学习方法:最新成果、挑战和机遇

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2022-07-05 DOI: 10.3390/jlpea12030037

Francesco Barchi, Emanuele Parisi, Andrea Bartolini, A. Acquaviva

引用次数: 0

±0.3V Bulk-Driven Fully Differential Buffer with High Figures of Merit ±0.3V大容量驱动的高性能全差分缓冲器

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2022-06-22 DOI: 10.3390/jlpea12030035

Manaswini Gangineni, J. Ramírez-Angulo, H. Vázquez-Leal, J. Huerta-Chua, A. López-Martín, R. Carvajal

引用次数: 2

Implementing a Timing Error-Resilient and Energy-Efficient Near-Threshold Hardware Accelerator for Deep Neural Network Inference 实现一种用于深度神经网络推理的时间误差弹性和节能的近阈值硬件加速器

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2022-06-06 DOI: 10.3390/jlpea12020032

N. D. Gundi, Pramesh Pandey, Sanghamitra Roy, Koushik Chakraborty

{"title":"Implementing a Timing Error-Resilient and Energy-Efficient Near-Threshold Hardware Accelerator for Deep Neural Network Inference","authors":"N. D. Gundi, Pramesh Pandey, Sanghamitra Roy, Koushik Chakraborty","doi":"10.3390/jlpea12020032","DOIUrl":"https://doi.org/10.3390/jlpea12020032","url":null,"abstract":"Increasing processing requirements in the Artificial Intelligence (AI) realm has led to the emergence of domain-specific architectures for Deep Neural Network (DNN) applications. Tensor Processing Unit (TPU), a DNN accelerator by Google, has emerged as a front runner outclassing its contemporaries, CPUs and GPUs, in performance by 15×–30×. TPUs have been deployed in Google data centers to cater to the performance demands. However, a TPU’s performance enhancement is accompanied by a mammoth power consumption. In the pursuit of lowering the energy utilization, this paper proposes PREDITOR—a low-power TPU operating in the Near-Threshold Computing (NTC) realm. PREDITOR uses mathematical analysis to mitigate the undetectable timing errors by boosting the voltage of the selective multiplier-and-accumulator units at specific intervals to enhance the performance of the NTC TPU, thereby ensuring a high inference accuracy at low voltage. PREDITOR offers up to 3×–5× improved performance in comparison to the leading-edge error mitigation schemes with a minor loss in accuracy.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45014526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

The Potential of SoC FPAAs for Emerging Ultra-Low-Power Machine Learning SoC FPAAs在新兴超低功耗机器学习中的潜力

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2022-06-06 DOI: 10.3390/jlpea12020033

J. Hasler

{"title":"The Potential of SoC FPAAs for Emerging Ultra-Low-Power Machine Learning","authors":"J. Hasler","doi":"10.3390/jlpea12020033","DOIUrl":"https://doi.org/10.3390/jlpea12020033","url":null,"abstract":"Large-scale field-programmable analog arrays (FPAA) have the potential to handle machine inference and learning applications with significantly low energy requirements, potentially alleviating the high cost of these processes today, even in cloud-based systems. FPAA devices enable embedded machine learning, one form of physical mixed-signal computing, enabling machine learning and inference on low-power embedded platforms, particularly edge platforms. This discussion reviews the current capabilities of large-scale field-programmable analog arrays (FPAA), as well as considering the future potential of these SoC FPAA devices, including questions that enable ubiquitous use of FPAA devices similar to FPGA devices. Today’s FPAA devices include integrated analog and digital fabric, as well as specialized processors and infrastructure, becoming a platform of mixed-signal development and analog-enabled computing. We address and show that next-generation FPAAs can handle the required load of 10,000–10,000,000,000 PMAC, required for present and future large fielded applications, at orders of magnitude of lower energy levels than those expected by current technology, motivating the need to develop these new generations of FPAA devices.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43142468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Methodology to Design Static NCL Libraries 一种设计静态NCL库的方法

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2022-06-06 DOI: 10.3390/jlpea12020031

Toi Le Thanh, Lac Truong Tri, Trang Hoang

{"title":"A Methodology to Design Static NCL Libraries","authors":"Toi Le Thanh, Lac Truong Tri, Trang Hoang","doi":"10.3390/jlpea12020031","DOIUrl":"https://doi.org/10.3390/jlpea12020031","url":null,"abstract":"The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43577609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Embedded Object Detection with Custom LittleNet, FINN and Vitis AI DCNN Accelerators 嵌入式目标检测与自定义littleet, FINN和Vitis AI DCNN加速器

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2022-05-20 DOI: 10.3390/jlpea12020030

Michal Machura, M. Danilowicz, T. Kryjak

{"title":"Embedded Object Detection with Custom LittleNet, FINN and Vitis AI DCNN Accelerators","authors":"Michal Machura, M. Danilowicz, T. Kryjak","doi":"10.3390/jlpea12020030","DOIUrl":"https://doi.org/10.3390/jlpea12020030","url":null,"abstract":"Object detection is an essential component of many systems used, for example, in advanced driver assistance systems (ADAS) or advanced video surveillance systems (AVSS). Currently, the highest detection accuracy is achieved by solutions using deep convolutional neural networks (DCNN). Unfortunately, these come at the cost of a high computational complexity; hence, the work on the widely understood acceleration of these algorithms is very important and timely. In this work, we compare three different DCNN hardware accelerator implementation methods: coarse-grained (a custom accelerator called LittleNet), fine-grained (FINN) and sequential (Vitis AI). We evaluate the approaches in terms of object detection accuracy, throughput and energy usage on the VOT and VTB datasets. We also present the limitations of each of the methods considered. We describe the whole process of DNNs implementation, including architecture design, training, quantisation and hardware implementation. We used two custom DNN architectures to obtain a higher accuracy, higher throughput and lower energy consumption. The first was implemented in SystemVerilog and the second with the FINN tool from AMD Xilinx. Next, both approaches were compared with the Vitis AI tool from AMD Xilinx. The final implementations were tested on the Avnet Ultra96-V2 development board with the Zynq UltraScale+ MPSoC ZCU3EG device. For two different DNNs architectures, we achieved a throughput of 196 fps for our custom accelerator and 111 fps for FINN. The same networks implemented with Vitis AI achieved 123.3 fps and 53.3 fps, respectively.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2022-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45864626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Low-Overhead Reinforcement Learning-Based Power Management Using 2QoSM 基于2QoSM的低开销强化学习电源管理

IF 2.1

Journal of Low Power Electronics and Applications Pub Date : 2022-05-19 DOI: 10.3390/jlpea12020029

Michael J. Giardino, D. Schwyn, Bonnie H. Ferri, A. Ferri

引用次数: 1