2008 58th Electronic Components and Technology Conference最新文献

Effects of warpage on fatigue reliability of solder bumps: Experimental and analytical studies 翘曲对焊料凸点疲劳可靠性的影响:实验和分析研究

2008 58th Electronic Components and Technology Conference Pub Date : 2010-04-22 DOI: 10.1109/TADVP.2010.2041451

W. Tan, I. C. Ume, Ying-Chang Hung, C. F. J. Wu

{"title":"Effects of warpage on fatigue reliability of solder bumps: Experimental and analytical studies","authors":"W. Tan, I. C. Ume, Ying-Chang Hung, C. F. J. Wu","doi":"10.1109/TADVP.2010.2041451","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2041451","url":null,"abstract":"Out-of-plane displacement (warpage) has been a major thermomechanical reliability concern for board-level electronic packages. Printed wiring board (PWB) and component warpage results principally from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may lead to severe solder bump reliability problems. In this research, the effect of initial PWB warpage on the low cycle thermal fatigue reliability of the solder bumps in plastic ball grid array (PBGA) packages was studied using experimental and analytical methods. A real-time projection moire warpage measurement system was used to measure the surface topology of PWBA samples at different temperatures. The thermal fatigue reliability of solder bumps was evaluated from experimental thermal cycling tests and finite element simulation results. Three-dimensional (3-D) models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different types of PBGAs mounted on PWBs. In order to improve the accuracy of FE results, the projection moire method was used to measure the initial warpage of PWBs, and this warpage was used as a geometric input to the FEM. The simulation results were validated and correlated with the experimental results obtained using the projection moire technique and accelerated thermal cycling tests. An advanced prediction model was generated to predict board level solder bump fatigue life based on the initial PWB warpage, package dimensions and locations, and solder bump materials.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131203500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Novel nonconductive adhesives/films with carbon nanotubes for high performance interconnects 用于高性能互连的新型碳纳米管非导电胶粘剂/薄膜

2008 58th Electronic Components and Technology Conference Pub Date : 2009-08-18 DOI: 10.1109/TCAPT.2009.2014742

Hongjin Jiang, M. Yim, K. Moon, C. Wong

引用次数: 9

Methodology for modeling substrate warpage using copper trace pattern implementation 使用铜痕迹模式实现的基板翘曲建模方法

2008 58th Electronic Components and Technology Conference Pub Date : 2009-07-24 DOI: 10.1109/TADVP.2009.2023464

L. McCaslin, S. Yoon, Hangyu Kim, S. Sitaraman

{"title":"Methodology for modeling substrate warpage using copper trace pattern implementation","authors":"L. McCaslin, S. Yoon, Hangyu Kim, S. Sitaraman","doi":"10.1109/TADVP.2009.2023464","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2023464","url":null,"abstract":"The current trend in the electronics industry is to decrease the size of electronic components while attempting to increase processing power and performance. This is leading to increased interest in thinner printed wiring boards and finer line widths and wire pitches. However, these goals can be hindered by the occurrence of warpage in the manufacturing and assembly process of electronic packages from mismatches in thermomechanical properties of the materials used. Warpage can be problematic as it leads to misalignments during package assembly, reduced tolerances, and a variety of operational failures. Current warpage prediction techniques utilize volume averaging to estimate material properties in layers of copper mixed with interlayer dielectric material. These techniques use copper percentages for an entire layer and do not account for trace orientation. This paper describes the development of a new methodology to predict the warpage of a particular substrate. The developed methodology accounts for both the trace pattern planar density and planar orientation in material property calculations for each layer of a multi-layer substrate. This process has been used to calculate the warpage of actual substrates and the results of using the developed methodology are shown to agree well with experimental data.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115396671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Robust design of third level packaging in portable electronics: Solder joint reliability under dynamic mechanical loading 便携式电子产品中第三级封装的稳健设计:动态机械载荷下的焊点可靠性

2008 58th Electronic Components and Technology Conference Pub Date : 2009-07-21 DOI: 10.1109/TCAPT.2009.2014258

Sridhar Canumalla, TI Boulevard

引用次数: 0

Synthesizing SPICE-compatible models of power delivery networks with resonance effect by time-domain waveforms 利用时域波形合成具有谐振效应的输电网络spice兼容模型

2008 58th Electronic Components and Technology Conference Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4606964

Chen-Chao Wang, C. Kuo, Hung-Hsiang Cheng, C. Chiu, C. Hung

引用次数: 1

Laser processing of 3-D structures for embedded and integrated components: An application of flexible and printable nanomaterials in microelectronics 嵌入式和集成元件三维结构的激光加工:柔性和可打印纳米材料在微电子学中的应用

2008 58th Electronic Components and Technology Conference Pub Date : 2008-06-24 DOI: 10.1109/ECTC.2008.4550010

R. Das, F. Egitto, T. Antesberger, F. Marconi, How T. Lin, J. Lauffer, V. Markovich

{"title":"Laser processing of 3-D structures for embedded and integrated components: An application of flexible and printable nanomaterials in microelectronics","authors":"R. Das, F. Egitto, T. Antesberger, F. Marconi, How T. Lin, J. Lauffer, V. Markovich","doi":"10.1109/ECTC.2008.4550010","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550010","url":null,"abstract":"This paper discusses laser processing of polymer nanocomposites and sol-gel thin films. In particular, recent developments on vertical multilayer embedded capacitors are highlighted. A variety of flexible, transperent nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on copper, or ITO, or organic substrates by large area (330 mm x 470 mm, or 495 mm x 610 mm) liquid coating processes. A frequency-tripled Nd:YAG laser operating at a wavelength of 355 nm was used for the micromachining study. The micromachining was used to generate arrays of variable-thickness capacitors from the nanocomposites. The resultant thickness of the capacitors depends on the number of laser pulses applied. Laser micromachining was also used to make long, deep multiple channels from a capacitance layer. Spacings between two channels act as individual vertical capacitors, and parallel connection eventually produces vertical multilayer capacitors. Optical phototgraphs and SEM micrographs were used to view spacings/channels in the coatings. In the case of sol-gel thin films, micromachining results in various surface morphologies. It can make a \"wavy\" random 3-D structure, or can make an array of regular 3D patterns (spirals/lines) depending on laser fluence. Altogether, this is a new direction for development of multifunctional nanomaterials.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130448408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Reliability of wafer level chip scale packages (WL-CSP) under dynamic loadings 动态负载下晶圆级芯片级封装(WL-CSP)的可靠性

2008 58th Electronic Components and Technology Conference Pub Date : 2008-05-27 DOI: 10.1109/ECTC.2008.4550222

Y. Lee, P. Crosbie, M. Brown, A. Zbrzezny

引用次数: 11

Cost-competitive RF wafer test methodology for high volume production of complex RF ICs 具有成本竞争力的射频晶圆测试方法，用于复杂射频集成电路的大批量生产

2008 58th Electronic Components and Technology Conference Pub Date : 2008-05-27 DOI: 10.1109/ECTC.2008.4550136

A. Paganini, M. Slamani, H. Ding, J. Ferrario, N. Na

引用次数: 5

The superior drop test performance of SAC-Ti solders and its mechanism SAC-Ti焊料优越的跌落试验性能及其机理

2008 58th Electronic Components and Technology Conference Pub Date : 2008-05-27 DOI: 10.1109/ECTC.2008.4550011

Weiping Liu, Paul Bachorik, N. Lee

引用次数: 23

All-copper chip-to-substrate interconnects: Bonding, testing, and design for electrical performance and thermo-mechanical reliability 全铜芯片到衬底互连:电气性能和热机械可靠性的键合，测试和设计

2008 58th Electronic Components and Technology Conference Pub Date : 2008-05-27 DOI: 10.1109/ECTC.2008.4549952

T. Osborn, A. He, H. Lightsey, P. Kohl

{"title":"All-copper chip-to-substrate interconnects: Bonding, testing, and design for electrical performance and thermo-mechanical reliability","authors":"T. Osborn, A. He, H. Lightsey, P. Kohl","doi":"10.1109/ECTC.2008.4549952","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549952","url":null,"abstract":"A novel fabrication process has been developed and characterized to create all-copper chip-to-substrate input/output (I/O) connections. Electroless copper plating followed by low temperature annealing in a nitrogen environment was used to create an all-copper bond between copper pillars. The bond strength for the all-copper structure exceeded 165 MPa after annealing at 180degC. During the anneal process, a significant microstructural transformation in the bonded copper-copper interface was observed. The changes were correlated to an increase in the bond strength. The process was characterized with respect to in-plane misalignment of bond sites. Significant planar misalignment, greater than the diameter of the pillars, could be tolerated. Through-plane mismatches between the pillars (pillar gap) as large as 65 mum could be overcome resulting in good pillar-to- pillar bonding. Successful silicon-on-FR4 bonding was achieved with no degradation of the organic board. The mechanical compliance and electrical performance of copper pillar chip-to-substrate interconnects has been modeled. The optimum pillar design is a trade-off between the mechanical compliance of the copper pillars and parasitic electrical effects. Copper pillars with a diameter of 48 mum to 100 mum and height of 508 mum to 657 mum are mechanically compliant and have parasitic inductance and capacitance less than 300 pH and 8.8 fF, respectively. A polymer collar improves the design space to 38 mum to 100 mum diameter and height from 441 mum to 617 mum.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127220076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8