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[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21最新文献

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A New Rapid Prototyping Firmware (RPF) Tool 一个新的快速成型固件(RPF)工具
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI: 10.1145/62504.62671
M. Andrews, F. Lam
{"title":"A New Rapid Prototyping Firmware (RPF) Tool","authors":"M. Andrews, F. Lam","doi":"10.1145/62504.62671","DOIUrl":"https://doi.org/10.1145/62504.62671","url":null,"abstract":"Microprogramming has progressed from a method for systematically designing control units to its wide-spread application to the design, emulation, analysis, and implementation of instruction sets for general-purpose computers. The application was greatly enhanced through the family-oriented architectures of the IBM System 360 and on into the DEC PDP-11 family, culminating in the VAX family of machines. Today, systolic, VLSI, and VHSIC microarchitectures are demanding increased centralized microprogrammable control capability. However, microprogramming has always been a tedious, time consuming, difficult to verify and, therefore, costly exercise. A new rapid prototyping firmware (RPF) tool is described which ameliorates most of the problems.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123620645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On Approximation Algorithms For Microcode Bit Minimizationt 关于微码位最小化的近似算法
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI: 10.1109/MICRO.1988.639257
S. Ravi, Dechang Gu
{"title":"On Approximation Algorithms For Microcode Bit Minimizationt","authors":"S. Ravi, Dechang Gu","doi":"10.1109/MICRO.1988.639257","DOIUrl":"https://doi.org/10.1109/MICRO.1988.639257","url":null,"abstract":"The bit (or width) minimization problem for microprograms is known to be NP-complete. Motivated by its practical importance, we address the question of obtaining near-optimal solutions. Two main results are presented. First, we establish a tight bound on the quality of solutions produced by algorithms which minimize the number of compatibility classes. Second, we show that the bit minimization problem has a polynomial time relative approximation algorithm only if the vertex coloring problem for graphs with n nodes can be approximated to within a factor of O(log n ) in polynomial time.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131434881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Evaluation Of A Concurrent Error Detection Method For Microprogrammed Control Units 一种微程序控制单元并发错误检测方法的评价
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI: 10.1145/62504.62507
A. Bailas, L. Kinney
{"title":"Evaluation Of A Concurrent Error Detection Method For Microprogrammed Control Units","authors":"A. Bailas, L. Kinney","doi":"10.1145/62504.62507","DOIUrl":"https://doi.org/10.1145/62504.62507","url":null,"abstract":"The need to detect faults, permanent, _ . . . transient and The method is general and application independent, i.e., it does not depend on the MCU used. The monitor circuit will differ of course since it depends on the error patterns generated by the faults considered. In this sense it differs from the design for concurrent error detection presented in [YEN 851. That paper followed the path of redesigning a specific MCU, the AMD2910, by adding redundancy in the form of coding and duplication. Error Detection Method for Microprogrammed","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"13 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116350002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Microarchitecture Modeling Through ADL 通过ADL进行微体系结构建模
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI: 10.1109/MICRO.1988.639265
Edil S. T. Fernandes
{"title":"Microarchitecture Modeling Through ADL","authors":"Edil S. T. Fernandes","doi":"10.1109/MICRO.1988.639265","DOIUrl":"https://doi.org/10.1109/MICRO.1988.639265","url":null,"abstract":"ADL is an Architecture Description Language that has been developed to model computer architectures at different levels of detail, as for instance, at the microarchitecture level. Target architectures described in ADL are processed by the support system of the language which generates an interpreter program related to the description of the target machine. The interpreter reproduces the behavior of the architecture being modeled, including the interpretation of the target code. In addition to a brief review of the language and the implementation details of its support system, this paper also shows some methods to deal with target machine parallelism, and the modeling of two microprogrammable machines.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123561865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multiple Instruction Issue And Single-chip Processors 多指令发布与单芯片处理器
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI: 10.1145/62504.62537
A. Pleszkun, G. Sohi
{"title":"Multiple Instruction Issue And Single-chip Processors","authors":"A. Pleszkun, G. Sohi","doi":"10.1145/62504.62537","DOIUrl":"https://doi.org/10.1145/62504.62537","url":null,"abstract":"In this paper we evaluate the performance of single-chip processors with multiple functional units. As a basis for our studies we use a processor model that is very similar to many of today's single-chip processors. Using this basic machine model, we investigate the performance that can be achieved if some limited form of multiple instruction issue is supported. For these investigations, we use 4 variants of the basic machine that represented different memory access times and branch execution times. In particular, we evaluate issuing 2 instructions per cycle and find that by restricting multiple instruction issue to load or branch instructions much of the same performance gains can be achieved as in the unrestricted form.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114754273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Microprogramming Support Tool For Pipelined Architectures 流水线体系结构的微编程支持工具
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI: 10.1109/MICRO.1988.639267
S. Molnar, Mark C. Surles
{"title":"A Microprogramming Support Tool For Pipelined Architectures","authors":"S. Molnar, Mark C. Surles","doi":"10.1109/MICRO.1988.639267","DOIUrl":"https://doi.org/10.1109/MICRO.1988.639267","url":null,"abstract":"We describe a software tool to aid the development of microcode for horizontal, pipelined architectures. The tool is a preprocessor for microcode source that allows the programmer full flexibility to optimize code, but removes many of the tedious and error-prone aspects of microprogramming. It automatically allocates floating-point registers, expands complex instructions, and analyzes code for pipeline-related errors.\u0000We have written a working version of the tool for the Weitek XL-8032 floating-point chip set, a horizontal architecture with pipelined sequencer and floating-point datapaths. Although the tool was designed for the XL architecture, the algorithms used are applicable to other parallel/pipelined architectures.\u0000This paper argues for the existence of such tools, summarizes the algorithms needed to analyze control and data flow in the presence of pipelining, and characterizes the tool's performance based on nine microcoded routines written for a real-time 3-D graphics system.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130450490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Flexible Processors: A Promising Application-specific Processor Design Approach 灵活处理器:一种有前途的应用特定处理器设计方法
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI: 10.1145/62504.62512
A. Wolfe, John Paul Shen
{"title":"Flexible Processors: A Promising Application-specific Processor Design Approach","authors":"A. Wolfe, John Paul Shen","doi":"10.1145/62504.62512","DOIUrl":"https://doi.org/10.1145/62504.62512","url":null,"abstract":"A new approach to application specific processor design is presented in this paper. Existing application specific processors are either based on existing general purpose processors or custom designed special purpose processors. The availability of a new technology, the Xilinx Logic Cell Array, presents the opportunity for a new alternative. The Flexible Processor Cell is a prototype of an extremely reconfigurable application specific processor. Flexible processors can potentially provide the performance advantages of special purpose processors as well as the cost advantages of general purpose processors. The flexible processor concept opens many potential areas for future research in processor architecture and implementation. This paper presents the design, implementation, and preliminary performance evaluation of an experimental flexible processor.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128642611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Mapping Of Micro Data Flow Computations Onto Parallel Microarchitectures 微数据流计算在并行微架构上的映射
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI: 10.1145/62504.62540
L. Shih, C. Papachristou
{"title":"Mapping Of Micro Data Flow Computations Onto Parallel Microarchitectures","authors":"L. Shih, C. Papachristou","doi":"10.1145/62504.62540","DOIUrl":"https://doi.org/10.1145/62504.62540","url":null,"abstract":"This paper presents a method for mapping computation algorithms to parallel machines architectures. The approach is based on a fine grain mapping system, FGMS, whose basic rationale is to achieve better matchings between computations and architectures. FGMS consists of four stages, i.e., data flow graph generation, vertical mapping into fine grain graphs, horizontal mapping across interconnected processors and instruction or microcode generation for individual processors.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132096229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Global Microcode Compaction Under Timing Constraints 时序约束下的全局微码压缩
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI: 10.1109/MICRO.1988.639269
B. Su, Jian Wang, J. Xia
{"title":"Global Microcode Compaction Under Timing Constraints","authors":"B. Su, Jian Wang, J. Xia","doi":"10.1109/MICRO.1988.639269","DOIUrl":"https://doi.org/10.1109/MICRO.1988.639269","url":null,"abstract":"Existing global microcode compaction algorithms have all been based on the assumption that the parallelism exploitation is constrained only by data dependency and resource limitation. However, the timing constraint also has great impact upon microcode compaction, thus it is highly necessary to study global microcode compaction under timing constraints. This paper conducts an analysis on the global timing problem, modifies the MO motion rules and presents an algorithm based on Trace Scheduling for global microcode compaction under timing constraints.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133445391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Control Store Implementation Of A High Performance VLSI CISC 一种高性能VLSI CISC控制存储的实现
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI: 10.1145/62504.62543
J. Chang, H. Chao, K. Lewis, M. Holland
{"title":"Control Store Implementation Of A High Performance VLSI CISC","authors":"J. Chang, H. Chao, K. Lewis, M. Holland","doi":"10.1145/62504.62543","DOIUrl":"https://doi.org/10.1145/62504.62543","url":null,"abstract":"The implementation of the μ-sequencer and the large loadable control store of a high performance CMOS 370 system [1] is described. The control store consists of two parts, a small on-chip control store and a main control store. A small on-chip control store keeps the first two control words of each μ-sequence. A large main control store contains the remaining control words of each μ-sequence. The small control store is implemented so that there is no need to include an extra pipeline stage to start an instruction execution in order to achieve a short cycle time. With a short cycle time, the access of the large control store takes at least two cycles to complete. In order to get one control word every cycle, the access to the control store is pipelined. A static μ-branch prediction scheme is used to generate the next μ-address ahead of the determination of a μ-branch. With this scheme, an effectively one-cycle access from a large loadable control store can be achieved without affecting the machine cycle time.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131597653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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