{"title":"The Proposal Of A Computing Model For Prototypes Of Microprogrammed Machines Solving Complex Problems","authors":"E. Binaghi, G. Pasi, G. Sechi","doi":"10.1109/MICRO.1988.639273","DOIUrl":"https://doi.org/10.1109/MICRO.1988.639273","url":null,"abstract":"Our research work concerns the definition of computational systems for the solution of complex scientific problems. In this work we present the analysis of a computing model for the definition and the implementation of microprogrammed prototypal machines. The computing model is expressed in terms of a system of equations. The structure and the control of a microprogrammed machine is directly implied by the formally defined properties of the system of equations.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124172285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. M. Mulder, Robert J. Portier, A. Srivastava, R. I. Velt
{"title":"Efficient Macro-code Emulation In Hardwired Pipelined Processors","authors":"J. M. Mulder, Robert J. Portier, A. Srivastava, R. I. Velt","doi":"10.1109/MICRO.1988.639261","DOIUrl":"https://doi.org/10.1109/MICRO.1988.639261","url":null,"abstract":"Traditionally microcoded computers have been the ideal machines for implementing scalable architectures. These machines easily implement application-specific functionality in microcode and they allow architecturally transparent variation of cost/performance by trading off application code, microcode, and hardware. In contrast, hardwired machines are intrinsically incapable of implementing scalability, because they only implement a single level of interpretation. Recent RISC designs have introduced architectural features which partly resolve the scalability issues. They implement architectural openendness to allow application-specific functionality to be added to the architecture (by means of coprocessors and special function units). Additionally they define functions which, depending on application, cost, and performance, can be implemented in hardware or, by means of emulation, in software.\u0000Although identical from an abstract point of view, scalability by means of microprogramming and by means of emulation on a hardwired machine is significantly different. This paper describes the emulation facility provided in SCARCE (SCalable ARChitecture Experiment), a streamlined architecture specifically designed for a wide range of embedded applications, requiring high performance. While architecturally transparent, this emulation facility operates with little overhead (8 cycles), adds three control registers, and is always interruptible. By increasing the hardware investment, the overhead could be decreased to 4 cycles per trap.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130506871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design Of A Testable Risc-to-cisc Control Architecture","authors":"Y. Malaiya, Sheng Feng","doi":"10.1109/MICRO.1988.639254","DOIUrl":"https://doi.org/10.1109/MICRO.1988.639254","url":null,"abstract":"A new control architecture is introduced. It is highly testable, and it will support both simple and complex instruction sets. The flexibility is achieved by use of allocable-storage (AS) blocks. An AS block may be assigned to the control part to hold the microcode, or it may be assigned to the data part to hold data or instructions.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"1018 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114058718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Microcode Real-time Executive For Numeric Support Nodes Distributed Within Embedded Networks","authors":"J. Bondi","doi":"10.1145/62504.62532","DOIUrl":"https://doi.org/10.1145/62504.62532","url":null,"abstract":"The mix of nodes within heterogeneous embedded networks typically includes some highly specialized, numerically oriented nodes particularly adept at efficient manipulation of regularly structured, multi-element array operands. Such “Array Processing” (AP) nodes usually serve other more general-purpose (GP) nodes.\u0000Local node-level control of each AP is maintained by a microcoded AP-resident executive program (APX). The APX is carefully microcoded and tuned to minimize overhead incurred by the computation-or-throughput-intensive tasks using or sharing AP resources.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130329409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Data-flow Driven Resource Allocation In A Retargetable Microcode Compiler","authors":"H. Feuerhahn","doi":"10.1145/62504.62674","DOIUrl":"https://doi.org/10.1145/62504.62674","url":null,"abstract":"A method for global resource allocation is described, which minimizes data movements and optimizes the use of resources like special purpose registers and functional units in complicated bus structures. The algorithm can deal with arbitrary flow graphs and hierarchies of nonrecursive procedures. It is based on a thorough data flow analysis of the source program and a description of the target architecture.\u0000The method has been implemented in a retargetable compiler with front-ends for the system implementation languages C and CDL2.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116983187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}