Mapping Of Micro Data Flow Computations Onto Parallel Microarchitectures

Abstract

This paper presents a method for mapping computation algorithms to parallel machines architectures. The approach is based on a fine grain mapping system, FGMS, whose basic rationale is to achieve better matchings between computations and architectures. FGMS consists of four stages, i.e., data flow graph generation, vertical mapping into fine grain graphs, horizontal mapping across interconnected processors and instruction or microcode generation for individual processors.