{"title":"微数据流计算在并行微架构上的映射","authors":"L. Shih, C. Papachristou","doi":"10.1145/62504.62540","DOIUrl":null,"url":null,"abstract":"This paper presents a method for mapping computation algorithms to parallel machines architectures. The approach is based on a fine grain mapping system, FGMS, whose basic rationale is to achieve better matchings between computations and architectures. FGMS consists of four stages, i.e., data flow graph generation, vertical mapping into fine grain graphs, horizontal mapping across interconnected processors and instruction or microcode generation for individual processors.","PeriodicalId":378625,"journal":{"name":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","volume":"280 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Mapping Of Micro Data Flow Computations Onto Parallel Microarchitectures\",\"authors\":\"L. Shih, C. Papachristou\",\"doi\":\"10.1145/62504.62540\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a method for mapping computation algorithms to parallel machines architectures. The approach is based on a fine grain mapping system, FGMS, whose basic rationale is to achieve better matchings between computations and architectures. FGMS consists of four stages, i.e., data flow graph generation, vertical mapping into fine grain graphs, horizontal mapping across interconnected processors and instruction or microcode generation for individual processors.\",\"PeriodicalId\":378625,\"journal\":{\"name\":\"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21\",\"volume\":\"280 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-01-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/62504.62540\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/62504.62540","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Mapping Of Micro Data Flow Computations Onto Parallel Microarchitectures
This paper presents a method for mapping computation algorithms to parallel machines architectures. The approach is based on a fine grain mapping system, FGMS, whose basic rationale is to achieve better matchings between computations and architectures. FGMS consists of four stages, i.e., data flow graph generation, vertical mapping into fine grain graphs, horizontal mapping across interconnected processors and instruction or microcode generation for individual processors.
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