Proceedings of 1994 VLSI Technology Symposium最新文献

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A compact inverted-spacer TFT for high-density SRAMs 用于高密度sram的紧凑反间隔TFT
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324435
J.R. Pfiester, J. Lin, K. Mocala, Y. Ku, J. Higman, T. McNelly, M. Blackwell, V. Kaushik, B. James, R. Hegde
{"title":"A compact inverted-spacer TFT for high-density SRAMs","authors":"J.R. Pfiester, J. Lin, K. Mocala, Y. Ku, J. Higman, T. McNelly, M. Blackwell, V. Kaushik, B. James, R. Hegde","doi":"10.1109/VLSIT.1994.324435","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324435","url":null,"abstract":"Polysilicon thin-film transistors (TFT) are typically used in high-density SRAMs due to their low standby power dissipation and high on/off current ratio. However, as the bitcell area continues to decrease for higher density SRAMs circuit applications, less space is available for integrating the TFT into the bitcell. In this paper, a new TFT structure is proposed which is self-aligned to the underlying NMOS device, thereby providing a compact load element that exhibits excellent device performance at reduced power-supply voltages. The inverted-spacer TFT channel is formed in a narrow poly-filled lateral cavity around the inside perimeter of the bulk NMOS polysilicon gate stack.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121286865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An ultra-thin fully depleted floating gate technology for 64 Mb flash and beyond 一种超薄的完全耗尽浮动栅极技术,适用于64mb及以上的闪存
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324375
S. Sato, K. Hakozaki, K. Azuma, K. Iguchi, K. Sakiyama
{"title":"An ultra-thin fully depleted floating gate technology for 64 Mb flash and beyond","authors":"S. Sato, K. Hakozaki, K. Azuma, K. Iguchi, K. Sakiyama","doi":"10.1109/VLSIT.1994.324375","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324375","url":null,"abstract":"In high density flash memories such as 8 Mb and 16 Mb, a stacked single transistor cell, which is programmed with channel hot-electron injection and erased with Fowler-Nordheim tunneling from the source side, is a key technology. However, cell size reduction and decrease of power consumption are required in order to realize higher density and 3 V-single power supply flash memories. In this paper, we propose a flash memory cell with an ultrathin and non-dope floating gate which is fully depleted and acts as dielectric film. Due to its dielectric nature, programming speed can be improved by factor two compared with a connectional cell. These characteristics can reduce power consumption of programming. Because the ultra-thin floating gate with thickness of about 100 /spl Aring/ minimizes field oxide loss, a cell size of 1.3 m/sup 2/ can be easily achieved, which is 25% smaller than a conventional one with a same design rule. Furthermore, a possibility of replacing ONO interpoly dielectric film by a single layer oxide film with thickness of 100/spl Aring/ is demonstrated.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126116208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploring the limits of cycle time for VLSI processing 探索VLSI处理的周期时间限制
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324392
R. Doering, D. Reed
{"title":"Exploring the limits of cycle time for VLSI processing","authors":"R. Doering, D. Reed","doi":"10.1109/VLSIT.1994.324392","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324392","url":null,"abstract":"Theoretical cycle time of 17.5 hours has been demonstrated on 13-mask 0.35-/spl mu/m CMOS using 100% single-wafer processing and real-time process control. The process time during which \"the wafer state was being altered\" was only 9.4 hours. In this experiment, total cycle time of less than 72 hours (3 days) was demonstrated. Under ideal conditions (e.g., no queues) it should be possible to manufacture advanced ICs with cycle times as short as approximately 2 hours per mask level.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123606121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
0.15 /spl mu/m ArF excimer laser lithography using top surface imaging with high contrast silylation agent B(DMA)DS 采用高对比度硅化剂B(DMA)DS顶面成像的0.15 /spl μ m ArF准分子激光光刻技术
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324439
T. Ohfuji, N. Aizaki
{"title":"0.15 /spl mu/m ArF excimer laser lithography using top surface imaging with high contrast silylation agent B(DMA)DS","authors":"T. Ohfuji, N. Aizaki","doi":"10.1109/VLSIT.1994.324439","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324439","url":null,"abstract":"The authors developed a room temperature liquid phase silylation process using Bis(dimethylamino)dimetylsilane (B[DMA]DS), which had been reported as the highest contrast silylation agent in the i-line DESIRE process. This paper describes the potential of the 193 nm lithography for 0.15 /spl mu/m rule and discuss process capabilities. Room temperature liquid phase silylation with B(DMA)DS was applied to 193nm ArF excimer laser lithography, 0.14 /spl mu/m resolution was acheived with a conventional binary mask. It is demonstrated that 193 nm is the most promising method for 1-4G DRAMs fabrication.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129035236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Data retention in ultra-thin-film-SOI DRAM with buried capacitor cell 埋式电容电池超薄膜soi DRAM的数据保留
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324388
T. Nishihara, H. Moriya, N. Ikeda, H. Aozasa, Y. Miyazawa
{"title":"Data retention in ultra-thin-film-SOI DRAM with buried capacitor cell","authors":"T. Nishihara, H. Moriya, N. Ikeda, H. Aozasa, Y. Miyazawa","doi":"10.1109/VLSIT.1994.324388","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324388","url":null,"abstract":"Data retention in DRAM cells with ultra-thin bonded SOI film is investigated using 256 kbit fully functional test chip of 0.4 /spl mu/m design rule. In order to minimize an accumulation of minority carriers in channel region, we adopt a PMOS cell transistor. As a result, a retention time of 47 seconds for 50% bit fail at 25/spl deg/C, which is determined by a subthreshold diffusion current in the cell transistor, is obtained. A possibility of further improvement in retention time is then discussed. An importance of an elimination of GIDL is also pointed out.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115574746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
0.1 /spl mu/m delta-doped MOSFET using post low-energy implanting selective epitaxy 0.1 /spl mu/m δ掺杂MOSFET低能植入后选择性外延
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324398
K. Noda, T. Uchida, T. Tatsumi, T. Aoyama, K. Nakajima, H. Miyamoto, T. Hashimoto, I. Sasaki
{"title":"0.1 /spl mu/m delta-doped MOSFET using post low-energy implanting selective epitaxy","authors":"K. Noda, T. Uchida, T. Tatsumi, T. Aoyama, K. Nakajima, H. Miyamoto, T. Hashimoto, I. Sasaki","doi":"10.1109/VLSIT.1994.324398","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324398","url":null,"abstract":"Delta-doped NMOSFETs with 0.1 /spl mu/m gate length were fabricated by using Post Low-energy Implanting Selective Epitaxy (PLISE). Non-doped epitaxial channel layers were grown by UHV-CVD after BF/sub 2/ ion implanting at 10 keV. The delta-shaped doping configuration suppresses short-channel effects and reduces the junction capacitance. It allows the switching speed one and a half times faster than conventional approaches. The minimum gate delay is 7.2 ps at 2.5 V for an NMOS ring oscillator with a 10 /spl mu/m gate width and a 1 K/spl Omega/ load.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125861239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS 用新型低介电SiOF层间膜降低高速/低功耗亚半微米CMOS的布线电容
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324378
J. Ida, M. Yoshimaru, T. Usami, A. Ohtomo, K. Shimokawa, A. Kita, M. Ino
{"title":"Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS","authors":"J. Ida, M. Yoshimaru, T. Usami, A. Ohtomo, K. Shimokawa, A. Kita, M. Ino","doi":"10.1109/VLSIT.1994.324378","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324378","url":null,"abstract":"In sub-half micron CMOS, reduction of wiring capacitance is a key issue to improve the circuit performance because the ratio of wiring delay to total delay is increasing. In order to reduce the wiring capacitance, applying low dielectric materials to ULSI is most effective and developments of low dielectric materials have been reported recently. However, there have been no studies of applying those to sub-half micron CMOS. In this study, it is reported for the first time that the new low dielectric material \"SiOF\" which has been proposed previously has been applied to sub-half micron CMOS and the improvement of circuit performance has been confirmed. Moreover, it is clearly demonstrated that the SiOF film is inevitable to improve the circuit speed of 0.35 /spl mu/m CMOS with the scaling trend. Also, it is emphasized that the reduction of wiring capacitance with SiOF film is important from the viewpoint of power reduction in sub-half micron CMOS.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122579831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Semiconductor technology crisis and challenges towards the year 2000 面向2000年的半导体技术危机与挑战
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324404
S. Kohyama
{"title":"Semiconductor technology crisis and challenges towards the year 2000","authors":"S. Kohyama","doi":"10.1109/VLSIT.1994.324404","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324404","url":null,"abstract":"Continuing device miniaturization results in higher packing density and higher fabrication cost, thus requires high ROI products utilizing complex design capability. Usually complex design requires higher abstraction in order to cope with the design scale, on the other hand, because of the critical device characteristics and interconnect phenomena, technology dependent design is also necessary. In addition to performance and crosstalk requirement, power limitation including electromigration should be appropriately simulated. Packaging is another important differentiater and large cost factor. Testing is now often a critical path, and also suffering from cost burden. It should be noted that testing is a part of the design effort, but limits manufacturability considerably. Semiconductor vendors will become more and more solution providers rather than component suppliers, thus should cover system level design to all way down to manufacturing in various different segments. However, a single company can never achieve such a goal alone, that is why vertical and horizontal alliances have started to make sense. The answer to the challenges are global standardizations and alliance/partnership models in various different manners.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122042656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Novel deep sub-quarter micron PMOSFETs with ultra-shallow junctions utilizing boron diffusion from poly-Si/oxide(BDSOX) 利用多晶硅/氧化物(BDSOX)硼扩散的新型超浅结深亚四分之一微米pmosfet
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324397
M. Togo, T. Mogami, K. Uwasawa, T. Kunio
{"title":"Novel deep sub-quarter micron PMOSFETs with ultra-shallow junctions utilizing boron diffusion from poly-Si/oxide(BDSOX)","authors":"M. Togo, T. Mogami, K. Uwasawa, T. Kunio","doi":"10.1109/VLSIT.1994.324397","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324397","url":null,"abstract":"A new ultra-shallow junction fabrication process, utilizing boron diffusion from poly-silicon/oxide(BDSOX) structure, has been developed for deep sub-quarter micron PMOSFETs. Ultra-shallow (<30-40 nm) and high concentration (>5/spl times/10/sup 1/9 cm/sup 3/) junctions have been realized. Short channel effects were significantly suppressed and good electrical characteristics were obtained for deep sub-quarter micron PMOSEETs by utilizing the BDSOX process. This new process is compatible with the conventional CMOS process.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130924791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low parasitic resistance technologies with NES-SAC and SWT-CVD process for low supply voltage, high speed BiCMOS SRAMs 用于低电源电压、高速 BiCMOS SRAM 的 NES-SAC 和 SWT-CVD 工艺的低寄生电阻技术
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324436
Y. Ishigaki, H. Kuriyama, H. Honda, Y. Kohno, J. Tsuchimoto, S. Sakamori, A. Kinoshita, T. Hirose, S. Ohbayashi, M. Ashida, H. Matsuo, H. Miyoshi
{"title":"Low parasitic resistance technologies with NES-SAC and SWT-CVD process for low supply voltage, high speed BiCMOS SRAMs","authors":"Y. Ishigaki, H. Kuriyama, H. Honda, Y. Kohno, J. Tsuchimoto, S. Sakamori, A. Kinoshita, T. Hirose, S. Ohbayashi, M. Ashida, H. Matsuo, H. Miyoshi","doi":"10.1109/VLSIT.1994.324436","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324436","url":null,"abstract":"The nitride etch stop self align contact (NES-SAC) process, the single wafer type (SWT-CVD) process and the modified fabrication method of bipolar transistors suitable for low supply voltage, high performance BiCMOS SRAMs are presented. Using these technologies, very small resistance contacts, small resistance ground lines and high performance bipolar transistors with small emitter resistance are achieved. Hence, a 1 M (64k/spl times/18) TTL SRAM with stable cell operation at 1.8 V and high speed access time of 7.8 ns is realized. These technologies are effective for the sub-half micron low supply voltage BICMOS SRAMs.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130968995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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