Proceedings of 1994 VLSI Technology Symposium最新文献_第2页

Performance fluctuations of 0.10 /spl mu/m MOSFETs-limitation of 0.1 /spl mu/m ULSIs mosfet的性能波动为0.10 /spl mu/m, ulsi的限制为0.1 /spl mu/m

Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324401

T. Mizuno, M. Iwase, H. Niiyama, T. Shibata, K. Fujisaki, T. Nakasugi, A. Toriumi, Y. Ushiku

引用次数: 9

Novel annular illumination using controlled phase and transparency 采用可控相位和透明的新型环形照明

Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324438

T. Sugihara, S. Mori, T. Fukushima, J. Takagi

引用次数: 0

A 0.5 /spl mu/m technology for advanced microcontroller applications 0.5 /spl mu/m技术，适用于高级微控制器应用

Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324374

U. Sharma, Kuo-Tung Chang, M. Woo, Ko-Min Chang, J.R. Yeargain

引用次数: 0

A low donor concentration retrograde profile Si bipolar transistor for low-temperature BiCMOS LSI's 用于低温BiCMOS LSI的低供体浓度逆行型硅双极晶体管

Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324408

K. Imai, Y. Kinoshita, T. Yamazaki, T. Tatsumi, T. Tashiro

引用次数: 0

1/f noise in poly-Si MOSFET and strong correlation with oxide traps and grain boundaries 多晶硅MOSFET中的1/f噪声与氧化物陷阱和晶界有很强的相关性

Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324442

T. Hashimoto, M. Aoki, T. Yamanaka, Y. Kamigaki, T. Nishida

引用次数: 4

An ultra-low power 0.1 /spl mu/m CMOS 超低功耗0.1 /spl μ m CMOS

Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324403

Y. Mii, S. Wind, Y. Taur, Y. Lii, D. Klaus, J. Bucchignano

引用次数: 20

Gate oxynitride grown in nitric oxide (NO) 在一氧化氮(NO)中生长的栅极氮化氧

Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324433

Y. Okada, P. Tobin, K. Reid, R. Hegde, B. Maiti, S. Ajuria

引用次数: 17

La doped PZT films for gigabit DRAM technology 用于千兆DRAM技术的La掺杂PZT薄膜

Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324412

Jiyoung Kim, R. Khamankar, C. Sudhama, B. Jiang, J. Lee, P. Maniar, R. Moazzami, R. Jones, C. Mogab

引用次数: 4

Trench isolation technology with 1 /spl mu/m depth n- and p-wells for a full-CMOS SRAM cell with a 0.4 /spl mu/m n/sup +p/sup +/ spacing 沟槽隔离技术，深度为1 /spl mu/m的n-和p-井，适用于间距为0.4 /spl mu/m的n/sup +p/sup +/的全cmos SRAM电池

Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324437

K. Ishimaru, H. Gojohbori, H. Koike, Y. Unno, M. Sai, F. Matsuoka, M. Kakumu

引用次数: 5

High speed sub-halfmicron flash memory technology with simple stacked gate structure cell 采用简单堆叠栅结构单元的高速亚半微米闪存技术

Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324381

S. Mori, E. Sakagami, Y. Yamaguchi, E. Kamiya, M. Tanimoto, H. Tsunoda, K. Hisatomi, H. Egawa, N. Arai, Y. Hiura, K. Yoshikawa, K. Hashimoto

{"title":"High speed sub-halfmicron flash memory technology with simple stacked gate structure cell","authors":"S. Mori, E. Sakagami, Y. Yamaguchi, E. Kamiya, M. Tanimoto, H. Tsunoda, K. Hisatomi, H. Egawa, N. Arai, Y. Hiura, K. Yoshikawa, K. Hashimoto","doi":"10.1109/VLSIT.1994.324381","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324381","url":null,"abstract":"This paper describes the novel process/device technology for high speed sub-halfmicron flash memories with 0.4 /spl mu/m design rules. Some new structures and operating methods for future flash memories have been proposed. However, the most suitable structure to realize large memory capacity for magnetic disk replacement will be different from that for fast random access speed for EPROM replacement, flash-memory-embedded logic devices, and other high speed applications. To realize high speed random access operation, conventional NOR-type flash memory technology with CHE program and source erase scheme will be the most suitable because of its simple fabrication process, relatively small cell size, sufficiently high read current, and relatively low operation voltages for program and erase procedures. The low voltage program/erase operation results in high performance peripheral transistors. On the other hand, NAND flash EEPROM will be the most suitable for low-cost large memory capacity applications. This paper, for the first time, demonstrates the scalability of cell gate length down to 0.4 /spl mu/m for simple stacked gate NOR flash cell.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127528283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4