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Proceedings of 1994 VLSI Technology Symposium最新文献

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ClF/sub 3/ gas compound for particle free contact hole etching 用于无颗粒接触孔蚀刻的ClF/sub - 3/气体化合物
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324393
S. Imai, T. Tamaki, S. Okada, M. Kubota, N. Nomura
{"title":"ClF/sub 3/ gas compound for particle free contact hole etching","authors":"S. Imai, T. Tamaki, S. Okada, M. Kubota, N. Nomura","doi":"10.1109/VLSIT.1994.324393","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324393","url":null,"abstract":"We propose a novel contact hole etching process using gas phase reaction of ClF/sub 3/. Particle free etching can be achieved by suppressing polymer deposition on the chamber wall while maintaining high oxide/silicon selectivity. ClF/sub 3/ can simultaneously etch oxide and clean the chamber wall. The same chamber can be used to remove the damaged silicon layer after contact hole formation and additional plasma apparatus, which has been necessary in conventional etching, is eliminated. This technology ensures high yield and cost-effective contact hole etching.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120950976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultra-low contact resistance metallization by a silicidation technology employing a silicon capping layer for protection against contamination 采用硅化技术的超低接触电阻金属化，采用硅盖层防止污染
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324376
K. Yamada, K. Tomita, T. Ohmi
{"title":"Ultra-low contact resistance metallization by a silicidation technology employing a silicon capping layer for protection against contamination","authors":"K. Yamada, K. Tomita, T. Ohmi","doi":"10.1109/VLSIT.1994.324376","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324376","url":null,"abstract":"An ultra low contact resistance metallization process has been developed by employing Ta silicidation of Si contact surface by ion beam mixing through a tantalum film covered with a Si capping layer. The as-deposited Ta surface is protected in-situ by a very thin Si film in order to prevent the metal surface from being oxidized or contaminated during subsequent processing. As a result, completely native-oxide-free contact metallization has been established. By combining the oxide-free Si/metal-on-Si deposition and ultraclean ion implantation for ion mixing, an ultra low contact resistance of 3.3/spl times/10/sup -9/ (/spl Omega/ cm/sup 2/) has been achieved.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123426829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Dual (n/sup +p/sup +/) polycide gate technology using Si-rich WSi/sub x/ to exterminate lateral dopant diffusion 双(n/sup +p/sup +/)多晶硅栅极技术采用富硅WSi/sub x/来消除横向掺杂物扩散
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324429
T. Fujii, S. Hashimoto, T. Hori
{"title":"Dual (n/sup +p/sup +/) polycide gate technology using Si-rich WSi/sub x/ to exterminate lateral dopant diffusion","authors":"T. Fujii, S. Hashimoto, T. Hori","doi":"10.1109/VLSIT.1994.324429","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324429","url":null,"abstract":"We have developed a new technology to solve the device degradation of the dual-polycide-gate N/sup +P/sup +/ CMOS due to the lateral dopant diffusion in the silicide. This was realized by using a Si-rich WSi/sub x/ without any other process steps. With this technology, no significant threshold voltage shift was observed in PMOS even after 900/spl deg/C annealing. This is because the grain growth of the excess Si in the WSi/sub x/ blocks the lateral dopant diffusion path.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"15 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125275791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ultrafast low-power operation of p/sup +/-n/sup +/ double-gate SOI MOSFETs p/sup +/-n/sup +/双栅SOI mosfet的超快低功耗工作
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324402
T. Tanaka, K. Suzuki, H. Horie, T. Sugii
{"title":"Ultrafast low-power operation of p/sup +/-n/sup +/ double-gate SOI MOSFETs","authors":"T. Tanaka, K. Suzuki, H. Horie, T. Sugii","doi":"10.1109/VLSIT.1994.324402","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324402","url":null,"abstract":"Using direct bonded SOI wafers just 40 nm thick, we fabricated p/sup +/-n/sup +/ double-gate SOI MOSFETs. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. For Lg=0.19 /spl mu/m, we obtained an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V. These are the fastest reported values for this gate length. The high performance is attributed to the large drain current, the low series resistance, and the reduction of the parasitic drain junction capacitance.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116198644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Novel electrolysis-ionized-water cleaning technique for the chemical-mechanical polishing (CMP) process 用于化学机械抛光(CMP)工艺的新型电解-离子水清洗技术
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324368
H. Aoki, T. Nakajima, K. Kikuta, Y. Hayashi
{"title":"Novel electrolysis-ionized-water cleaning technique for the chemical-mechanical polishing (CMP) process","authors":"H. Aoki, T. Nakajima, K. Kikuta, Y. Hayashi","doi":"10.1109/VLSIT.1994.324368","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324368","url":null,"abstract":"Recently, chemical-mechanical-polishing (CMP) technology has become more and more important as device packing-density has increased. This is because the CMP of interlayer dielectrics realizes global planarization resulting in multi-level interconnections with finer pitches. However, effective wafer surface cleaning for particles and contamination is needed because slurries with colloidal silica particles are used during the CMP processing. Though wafer cleaning by using acid or alkaline chemicals was generally used, an increasing amount of the chemicals will cause ecological problems. We have reported that the electrolysis ionized water cleaning technique was useful for the removal of particles and metal contamination. This indicates a ecologically-safe cleaning process without using direct chemical reactions. This paper presents a reductive electrolysis ionized water cleaning technique for application to CMP processes, which includes a spin rinser system. Damage-free cleaning for an Al damascene process after the CMP is demonstrated for the first time.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126981361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Scaling of tunnel oxide thickness for flash EEPROMs realizing stress-induced leakage current reduction 实现应力诱发泄漏电流减小的闪存eeprom隧道氧化层厚度的缩放
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324384
H. Watanabe, S. Aritome, G. Hemink, T. Maruyama, R. Shirota
{"title":"Scaling of tunnel oxide thickness for flash EEPROMs realizing stress-induced leakage current reduction","authors":"H. Watanabe, S. Aritome, G. Hemink, T. Maruyama, R. Shirota","doi":"10.1109/VLSIT.1994.324384","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324384","url":null,"abstract":"It has been reported that the tunnel oxide of flash E/sup 2/PROM is spoiled by the write/erase sequence of high-field stress and that leakage current (J/sub leak/)is induced at lower voltage, which deteriorates retention time and limits the tunnel oxide thickness of E/sup 2/PROM/sup ./ In order to scale down the tunnel oxide thickness, this paper proposes two new approaches to decrease the leakage current. One is the decreasing impurity concentration in the floating gate poly-Si. The other is to lower annealing process temperature after the floating gate formation. These reduction of J/sub leak/ is more remarkable as the tunnel oxide thickness is thinner. As a result, the tunnel oxide can be scaled down to 6 nm by decreasing gate poly-Si concentration to about 5/spl times/10/sup 19/cm/sup -3/ and lowering annealing temperature to less than 900/spl deg/C. These process will become the key technology to realize 64 Mb E/sup 2/PROM and beyond.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"80 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116353130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Sub-quarter micron copper interconnects through dry etching process and its reliability 亚四分之一微米铜互连干刻蚀工艺及其可靠性
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324379
Y. Igarashi, T. Yamanobe, H. Jinbo, T. Ito
{"title":"Sub-quarter micron copper interconnects through dry etching process and its reliability","authors":"Y. Igarashi, T. Yamanobe, H. Jinbo, T. Ito","doi":"10.1109/VLSIT.1994.324379","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324379","url":null,"abstract":"Copper is the major candidate material of post-Al alloys in deep sub-micron region, because of low resistivity and long electromigration lifetime. Recently, ion milling and chemical mechanical polishing (CMP) have been applied to fine Cu interconnects, and these techniques can avoid the difficulty of etching Cu caused by hardly subliming etching-products. However, these are not necessarily the well-established technique for ULSI process. Our approach is modification of the high temperature dry etching, which includes the self-aligned passivation technique. In this work, we have formed TiN/Cu/TiN multilayered interconnects of sub-quarter micron width using the modified dry etching technique, and evaluated the resistance to electromigration damage (EMD).<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115776711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Consumers on a chip 芯片上的消费者
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324405
C. Ledbetter
{"title":"Consumers on a chip","authors":"C. Ledbetter","doi":"10.1109/VLSIT.1994.324405","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324405","url":null,"abstract":"The telecommunications technology now exists to provide customers with intelligent instruments that offer them readier access to an increasingly intelligent global network, and greater control over the services it provides. The question is whether this technology can be converted into products that meet customer needs and expectations. The hardware and software are now available to supply real-time, two-way voice, data and messaging services any time the customer needs them, from any location, using wired or wireless networks. Moreover, the communications instrument at the customer's disposal-whether corded or cordless, cellular or video-will contain intelligence that allows the customer to summon services tailored to that customer's individual needs.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130065212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hydrogen-radical-balanced steam oxidation for growing ultra-thin high-reliability gate oxide films 氢自由基平衡蒸汽氧化法制备超薄高可靠性栅极氧化膜
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324431
K. Ohmi, K. Nakamura, T. Futatsuki, T. Ohmi
{"title":"Hydrogen-radical-balanced steam oxidation for growing ultra-thin high-reliability gate oxide films","authors":"K. Ohmi, K. Nakamura, T. Futatsuki, T. Ohmi","doi":"10.1109/VLSIT.1994.324431","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324431","url":null,"abstract":"A unique oxidation technology has been developed, in which oxidation proceeds in competition with reduction by active hydrogen. Active hydrogen in the oxidizing ambient immediately attacks weak spots formed in the oxide in the midst of oxidation processes, allowing only high-integrity oxide to survive and grow. In order to preserve a contamination-free Si-SiO/sub 2/ interface up to the start of oxidation, ultra clean chemical oxide is utilized as a passivation film. As a result, gate oxide films as thin as 5 nm featuring high breakdown fields and excellent endurance against charge injection have been obtained. The purpose of this paper is to report on the state-of-the-art ultra clean thermal oxidation technology.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117335060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ultrathin (<30 /spl Aring/) storage capacitor dielectrics prepared by in-situ multiprocessing and low pressure rapid thermal N/sub 2/O reoxidation 采用原位多工艺和低压快速热N/sub /O再氧化制备超薄(<30 /spl /)存储电容器介质
Proceedings of 1994 VLSI Technology Symposium Pub Date : 1994-06-07 DOI: 10.1109/VLSIT.1994.324410
G. Yoon, J. Kim, L. K. Han, J. Yan, Dim-Lee Kwong
{"title":"Ultrathin (<30 /spl Aring/) storage capacitor dielectrics prepared by in-situ multiprocessing and low pressure rapid thermal N/sub 2/O reoxidation","authors":"G. Yoon, J. Kim, L. K. Han, J. Yan, Dim-Lee Kwong","doi":"10.1109/VLSIT.1994.324410","DOIUrl":"https://doi.org/10.1109/VLSIT.1994.324410","url":null,"abstract":"High quality, ultrathin (<30 /spl Aring/) SiO/sub 2/-Si/sub 3/N/sub 4/ (ON) stacked film capacitors have been fabricated by in-situ multiprocessing and low pressure rapid-thermal N/sub 2/O reoxidation (LRTNO) of Si/sub 3/N/sub 4/ films. Si/sub 3/N/sub 4/ film was deposited on the RTN-treated poly-Si by rapid-thermal chemical vapor deposition (RTCVD) using SiH/sub 4/ and NH/sub 3/, followed by in-situ low pressure rapid-thermal reoxidation in N/sub 2/O (LRTNO) or in O/sub 2/ (LRTO) ambient. Results show that ultrathin (T/sub ox,eq/=29 /spl Aring/) ON stacked film capacitors with LRTNO have excellent electrical properties and reliability.<<ETX>>","PeriodicalId":378128,"journal":{"name":"Proceedings of 1994 VLSI Technology Symposium","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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