2014 IEEE Fifth International Conference on Communications and Electronics (ICCE)最新文献_第5页

MultiStage ASIC implementation of the Mersenne Twister pseudorandom number generator MultiStage ASIC实现的Mersenne Twister伪随机数生成器

2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) Pub Date : 2014-10-07 DOI: 10.1109/CCE.2014.6916725

T. Le, Sricharan Narayanan

{"title":"MultiStage ASIC implementation of the Mersenne Twister pseudorandom number generator","authors":"T. Le, Sricharan Narayanan","doi":"10.1109/CCE.2014.6916725","DOIUrl":"https://doi.org/10.1109/CCE.2014.6916725","url":null,"abstract":"The development of cluster and parallel computers has increased the popularity of implementing the Monte Carlo (MC) computational method in medical and scientific applications. However, having access to these high-performance systems is not easy and a reasonable size system is not yet able to solve many popular Monte Carlo problems near real-time. The Field Programmable Gate Arrays (FPGAs) have been proved to be useful in speeding up the Monte Carlo algorithm since they are able to execute the problem with a high degree of parallelism. As the FPGA and ASIC are being applied for speeding up Monte Carlo simulations as well as for reducing energy consumption, the generation of pseudorandom number (PRN) by hardware becomes one of major developments. The speed in generating the random numbers and the quality of these numbers are main factors in enhancing the performance and accuracy of the method. In this paper, we present the design and implementation of a multistage pipelining-style Mersenne Twister (MT), one of the most widely used pseudorandom number generation method. By implementing the operations in 4 stages, our design is able to achieve throughput of 178 million, 228 million, and 338 million random numbers per second on 0.25 μm, 0.14 μm, and 90 nm processes, respectively. In theory, the implementation can be scaled up to 208 stages and so the throughput can be up to 18 billion random numbers per second.","PeriodicalId":377853,"journal":{"name":"2014 IEEE Fifth International Conference on Communications and Electronics (ICCE)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126722997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parallel Random Access Memory in a shared memory architecture 共享内存架构中的并行随机存取存储器

2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) Pub Date : 2014-10-07 DOI: 10.1109/CCE.2014.6916731

Tran Duc Linh, T. de Souza-Daw, T. Hoang, N. T. Dzung

{"title":"Parallel Random Access Memory in a shared memory architecture","authors":"Tran Duc Linh, T. de Souza-Daw, T. Hoang, N. T. Dzung","doi":"10.1109/CCE.2014.6916731","DOIUrl":"https://doi.org/10.1109/CCE.2014.6916731","url":null,"abstract":"Parallel algorithms can significantly speed up computing performance. However, parallel architecture often needs shared-memories for concurrent access. Conventionally, parallel memories are constructed as space-multiplexed memories with many memory chips connected in parallel. This architecture normally requires a large number of interconnects with potentially large routing delay and consumes massive area. This proposal develops a new memory component called Parallel Random Access Memory (P-RAM) with four identical parallel ports. This component is designed using VHDL hardware description language and emulated on Cyclone II FPGA. The P-RAM is not a conventional RAM memory since its four ports can be read and write concurrently. It can be used for many purposes such as shared memory for multiple processors in a parallel model. The design of the P-RAM component has been fully tested in both simulation and hardware integration with processors. Five simulation test cases were used to test all possible access cases of P-RAM and they all passed. The P-RAM is synthesized as combinations of logic elements (flip-flops and logic gates) instead of normal memory bits since it is a new component to the synthesis tool. lKB P-RAM take about 11,630 logic elements. The proposed P-RAM Parallel System has two instances (distinct copy) of the P-RAM component. One is used as shared instruction memory and the another is used as shared data memory. To demonstrate P-RAM operations, one port is used to observe data memory content and 3 CPUs are connected to the other ports of P-RAM component. Due to the FPGA chip resource limitation, the P-RAM instruction memory is built with only lKB size (32-bit data 8-bit address buses). The instruction code of the parallel algorithm is hard-coded in this memory by direct memory initialization. From this memory, the parallel algorithm of Finding the Maximum is run on all processors. The P-RAM data memory has 4-bit data and 4-bit address buses.","PeriodicalId":377853,"journal":{"name":"2014 IEEE Fifth International Conference on Communications and Electronics (ICCE)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124367471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Design of a parallel plate slot array antenna fed by a rectangular coaxial line 矩形同轴馈线平行板槽阵列天线的设计

2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) Pub Date : 2014-10-07 DOI: 10.1109/CCE.2014.6916737

J. Hirokawa, Hajime Nakamichi, M. Sano, M. Ando, Katsumori Sasaki, I. Oshima

引用次数: 0

Sparsely sampled functional magnetic resonance imaging using low-rank and sparsity constraints 使用低秩和稀疏性约束的稀疏采样功能磁共振成像

2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) Pub Date : 2014-10-07 DOI: 10.1109/CCE.2014.6916747

Hien M. Nguyen, G. Glover

引用次数: 2

GTP-based load model and virtualization gain for a mobile network's GGSN 基于gtp的移动网络GGSN负载模型和虚拟化增益

2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) Pub Date : 2014-10-07 DOI: 10.1109/CCE.2014.6916704

Florian Metzger, Christian Schwartz, T. Hossfeld

引用次数: 5

A game-theoretic framework for opportunistic transmission in wireless networks 无线网络中机会传输的博弈论框架

2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) Pub Date : 2014-10-07 DOI: 10.1109/CCE.2014.6916695

C. Phan

引用次数: 7

GENI: Large-scale distributed infrastructure for networking and distributed systems research GENI:用于网络和分布式系统研究的大规模分布式基础设施

2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) Pub Date : 2014-10-07 DOI: 10.1109/CCE.2014.6916696

M. Berman, C. Elliott, L. Landweber

引用次数: 15

Dual band hexagonal microstrip antenna loaded with hexagonal and cylindrical EBG 双频六角形微带天线加载六角形和圆柱形EBG

2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) Pub Date : 2014-10-07 DOI: 10.1109/CCE.2014.6916734

G. Karthikeya, Shravan Kaundinya, S. Hariprasad

引用次数: 5

Secret key management and dynamic security coding system 密钥管理和动态安全编码系统

2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) Pub Date : 2014-10-07 DOI: 10.1109/CCE.2014.6916762

Thi Huyen Trang Nguyen, J. Barbot

引用次数: 1

Is affective crowdsourcing reliable? 情感众包可靠吗?

2014 IEEE Fifth International Conference on Communications and Electronics (ICCE) Pub Date : 2014-10-07 DOI: 10.1109/CCE.2014.6916757

I. Hupont, Pierre R. Lebreton, T. Maki, E. Skodras, Matthias Hirth

引用次数: 5