Parallel Random Access Memory in a shared memory architecture

Abstract

Parallel algorithms can significantly speed up computing performance. However, parallel architecture often needs shared-memories for concurrent access. Conventionally, parallel memories are constructed as space-multiplexed memories with many memory chips connected in parallel. This architecture normally requires a large number of interconnects with potentially large routing delay and consumes massive area. This proposal develops a new memory component called Parallel Random Access Memory (P-RAM) with four identical parallel ports. This component is designed using VHDL hardware description language and emulated on Cyclone II FPGA. The P-RAM is not a conventional RAM memory since its four ports can be read and write concurrently. It can be used for many purposes such as shared memory for multiple processors in a parallel model. The design of the P-RAM component has been fully tested in both simulation and hardware integration with processors. Five simulation test cases were used to test all possible access cases of P-RAM and they all passed. The P-RAM is synthesized as combinations of logic elements (flip-flops and logic gates) instead of normal memory bits since it is a new component to the synthesis tool. lKB P-RAM take about 11,630 logic elements. The proposed P-RAM Parallel System has two instances (distinct copy) of the P-RAM component. One is used as shared instruction memory and the another is used as shared data memory. To demonstrate P-RAM operations, one port is used to observe data memory content and 3 CPUs are connected to the other ports of P-RAM component. Due to the FPGA chip resource limitation, the P-RAM instruction memory is built with only lKB size (32-bit data 8-bit address buses). The instruction code of the parallel algorithm is hard-coded in this memory by direct memory initialization. From this memory, the parallel algorithm of Finding the Maximum is run on all processors. The P-RAM data memory has 4-bit data and 4-bit address buses.