发布求助
文献互助 智能选刊 最新文献

2023 International Conference on Electronics Packaging (ICEP)最新文献

筛选
英文 中文
Investigation of Solder Resist Opening Uniformity on Flip Chip Substrate 倒装芯片衬底上阻焊剂开口均匀性的研究
2023 International Conference on Electronics Packaging (ICEP) Pub Date : 2023-04-19 DOI: 10.23919/ICEP58572.2023.10129669
Yuan-Chang Ni, W. Teng, Y. Pai, Carl Chen, Yu-Po Wang
{"title":"Investigation of Solder Resist Opening Uniformity on Flip Chip Substrate","authors":"Yuan-Chang Ni, W. Teng, Y. Pai, Carl Chen, Yu-Po Wang","doi":"10.23919/ICEP58572.2023.10129669","DOIUrl":"https://doi.org/10.23919/ICEP58572.2023.10129669","url":null,"abstract":"Good solder resist (SR) opening uniformity can effectively avoid electrical defect in the connection between the chip and substrate, including device short, open issue and bump crack issue. The main objective of this research is to propose an optimized process control to improve SR uniformity by controlling queue time through DOE test, including the queue time of tear off PET film after exposure, exposure to development queue time and development chemical renew time. Among them, queue time of tear off PET film after exposure were selected from 1min. to 20min. The exposure to development queue time was set to 1hr to 4hr. The development chemical renew timing was also set. The best SR opening uniformity was revealed by tolerance of opening size, which can be reduced from ±5um to ±3um when queue time of tear off PET film after exposure were set to ≤1min of tear off PET after exposure. The DOE test result sheds light in improving the performance between chip and IC substrate.","PeriodicalId":377390,"journal":{"name":"2023 International Conference on Electronics Packaging (ICEP)","volume":"270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115596355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Topology Optimization of a Thermal Conduction Block using the Thermal Bottleneck 利用热瓶颈的热传导块拓扑优化
2023 International Conference on Electronics Packaging (ICEP) Pub Date : 2023-04-19 DOI: 10.23919/ICEP58572.2023.10129728
Haruki Takei
{"title":"Topology Optimization of a Thermal Conduction Block using the Thermal Bottleneck","authors":"Haruki Takei","doi":"10.23919/ICEP58572.2023.10129728","DOIUrl":"https://doi.org/10.23919/ICEP58572.2023.10129728","url":null,"abstract":"This paper presents examples of topology optimization using the thermal Bottleneck (BN). It can be applied to optimization for Thermal Conduction Blocks (TCBs) such as heatsinks. A parameter named BN is defined as an inner product between a heat flux vector and a temperature gradient vector. Regions with high BN values show \"thermal bottleneck\" as its name implies. Conversely, ones with low BN values don’t contribute for heat dissipation of TCBs. This indicates the optimized shape of TCBs can be obtained by removing from the regions with lowest BN value. In this paper, a heatsink attached to a simple Electronic Control Unit (ECU) was divided into fine cuboids and optimized by removing some of them from lowest BN value after calculation of Computer Fluid Dynamics (CFD) software. As a result, an optimized heatsink with an average of 3.0% lower thermal resistance than the reference case for the same volume, and another with 27% smaller volume for the same thermal resistance were obtained, respectively.","PeriodicalId":377390,"journal":{"name":"2023 International Conference on Electronics Packaging (ICEP)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127538374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of Bi and In Elemental Addition in Solder Paste for DRAM Module Reliability Enhancement 提高DRAM模块可靠性的锡膏中添加Bi和In元素的研究
2023 International Conference on Electronics Packaging (ICEP) Pub Date : 2023-04-19 DOI: 10.23919/ICEP58572.2023.10129742
Yun-Ting Hsu, Yu Zou, Yi-Yu Chen, Min-Hua Chung, C.L. Gan, Fatima Macalalad, Shriram Harihara Subramanian
{"title":"Investigation of Bi and In Elemental Addition in Solder Paste for DRAM Module Reliability Enhancement","authors":"Yun-Ting Hsu, Yu Zou, Yi-Yu Chen, Min-Hua Chung, C.L. Gan, Fatima Macalalad, Shriram Harihara Subramanian","doi":"10.23919/ICEP58572.2023.10129742","DOIUrl":"https://doi.org/10.23919/ICEP58572.2023.10129742","url":null,"abstract":"Solder pastes with Bi and In elemental additions were studied by solder joint strength, physical failure analysis, and module reliability tests in this work. Bi-doped solder alloys were found to have stronger solder joints than SAC305 and SnAgCu-In. During the temperature cycling test, SnAgCu-In appeared the best in thermal reliability performance. Samples with Bi and without Bi were observed with different crack modes: trace cracks were found in Bi-doped, and fatigue cracks existed in samples without Bi.","PeriodicalId":377390,"journal":{"name":"2023 International Conference on Electronics Packaging (ICEP)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123737355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FOPOP Warpage Analysis for Package Design Optimization 包装设计优化中的FOPOP翘曲分析
2023 International Conference on Electronics Packaging (ICEP) Pub Date : 2023-04-19 DOI: 10.23919/ICEP58572.2023.10129706
Ken Zhang, V. Lin, Teny Shih, Andrew Kang, Yu-Po Wang
{"title":"FOPOP Warpage Analysis for Package Design Optimization","authors":"Ken Zhang, V. Lin, Teny Shih, Andrew Kang, Yu-Po Wang","doi":"10.23919/ICEP58572.2023.10129706","DOIUrl":"https://doi.org/10.23919/ICEP58572.2023.10129706","url":null,"abstract":"Compared with HBWPOP (High Bandwidth Package on Package), a FOPOP (Fan Out Package on Package) which adopts RDL structure to replace traditional substrate has the advantages of thin package profile, high electric al and thermal performance…etc. And it has been used as high-end AP for smartphone in recent years. But package warpage control for the FOPOP is becoming more challenges than general package due to thinner package thickness. Poor package warpage will impact quality results of SMT and stacking DRAM. Thus, a 15x15 mm package size without DRAM pre-stacking is studied in this paper. Various structural factors includes die thickness, Cu stud height, top and bottom RDL thickness that will impact package warpage performance were simulated and analyzed. Simulation and analysis results showed that top and bottom RDL thickness are significant factors affecting package warpage. Moreover, an optimized FOPOP structure was proposed and assembled actually. Then its package warpage was measured by shadow moiré and compared with simulation results. Both results includes warpage values and contours were simulation and meet warpage requirement.","PeriodicalId":377390,"journal":{"name":"2023 International Conference on Electronics Packaging (ICEP)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125374289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hybrid SnBi/SAC Low-Temperature Solder Bump 混合SnBi/SAC低温凸点焊料
2023 International Conference on Electronics Packaging (ICEP) Pub Date : 2023-04-19 DOI: 10.23919/ICEP58572.2023.10129653
A. Wu, Jui-Lin Chao, Yu-Yuan Lai, Chang-meng Wang
{"title":"Hybrid SnBi/SAC Low-Temperature Solder Bump","authors":"A. Wu, Jui-Lin Chao, Yu-Yuan Lai, Chang-meng Wang","doi":"10.23919/ICEP58572.2023.10129653","DOIUrl":"https://doi.org/10.23919/ICEP58572.2023.10129653","url":null,"abstract":"Assembling advanced electronic packaging at low temperature attracts attentions from the industry. One of the advantages is to reduce the warpage of dies and enhance long-term reliability of the chips. Although eutectic SnBi is considered a widely accepted low-temperature solder, Bi segregation after annealing drastically degrades the mechanical strength. In this study, two layers of materials, a pre-solder (Sn-0.3Ag-0.7 Cu, SAC0307) and a low temperature solder (Sn-56Bi-1Ag-0.2Cu, SB102) was reflowed sequentially to create a hybrid solder joint. The reflow temperatures were set as 170 and 190 oC, which are much lower than that of the SAC solder. Adding SAC0307 reduces the Bi content in the joint and lessens the formation of Bi-rich phase. Comparing with SB 102 joint, the hybrid bond shows increasing joint strength after aging. The facture surface indicates that hybrid joint exhibits ductile fracture mode while SB 102 joint shows brittle mode. The results prove that SAC0307/SB102 hybrid solder joint can be a promising candidate for low-temperature application for advanced electronic packaging.","PeriodicalId":377390,"journal":{"name":"2023 International Conference on Electronics Packaging (ICEP)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125536562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of High Temperature Lead-free Solders in the Al-95Zn + xSn Systems Al-95Zn + xSn体系高温无铅钎料的研制
2023 International Conference on Electronics Packaging (ICEP) Pub Date : 2023-04-19 DOI: 10.23919/ICEP58572.2023.10129708
A. Laksono, Y. Yen
{"title":"Development of High Temperature Lead-free Solders in the Al-95Zn + xSn Systems","authors":"A. Laksono, Y. Yen","doi":"10.23919/ICEP58572.2023.10129708","DOIUrl":"https://doi.org/10.23919/ICEP58572.2023.10129708","url":null,"abstract":"The high-temperature lead-free solder alloys of Al-95Zn with the modification of the addition of Sn have been investigated. Its proportion is used to adjust the metallographic microstructure, solidified precipitate phase, and liquidus temperature of the solder alloy. The characterization results, such as scanning electron microscope (SEM), energy dispersive spectrometer (EDS), X-ray diffraction (XRD), and differential scanning calorimeter (DSC), will be discussed in this study. The study results show that the Al-Sn-Zn-based alloy has (Zn)+β- Sn+(Al) precipitates when heat-treated at 900°C for 36 h. Its liquidus temperature of Al-95Zn + xSn is between 342-385°C, and increased Sn content will decrease its liquidus temperature.","PeriodicalId":377390,"journal":{"name":"2023 International Conference on Electronics Packaging (ICEP)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126875450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Semiconductor Package Design Flow and Platform Applied on Fan-out Chip on Substrate 基板上扇出芯片的半导体封装设计流程和平台
2023 International Conference on Electronics Packaging (ICEP) Pub Date : 2023-04-19 DOI: 10.23919/ICEP58572.2023.10129673
Youle Lin, K. Chang, H. Kuo, Chih-Yi Huang, Chen-Chao Wang
{"title":"Semiconductor Package Design Flow and Platform Applied on Fan-out Chip on Substrate","authors":"Youle Lin, K. Chang, H. Kuo, Chih-Yi Huang, Chen-Chao Wang","doi":"10.23919/ICEP58572.2023.10129673","DOIUrl":"https://doi.org/10.23919/ICEP58572.2023.10129673","url":null,"abstract":"The research and discussion in this paper, there are package design with the structure of FOCoS for an actual high-performance computing IC device with two ASIC chips. In the process of this actual project, the design platform named SiP-id (System-in-Package Intelligent Design) was used to complete the routings of ultra-high density I/O such as Fan-Out redistribution layer (RDL). Compared with the traditional design platform, it was greatly pull-in design cycle time. The design time and the accuracy of the design are improved obviously. In addition, this paper also delivers a lot of self-developed programs to link up the design and validation tools from different vendors.","PeriodicalId":377390,"journal":{"name":"2023 International Conference on Electronics Packaging (ICEP)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115258748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compensation of the Warpage of CVD Diamond Wafers using Intermediate Layers for Surface Activated Bonding 利用中间层表面活化键合补偿CVD金刚石片的翘曲
2023 International Conference on Electronics Packaging (ICEP) Pub Date : 2023-04-19 DOI: 10.23919/ICEP58572.2023.10129652
Junsha Wang, T. Suga
{"title":"Compensation of the Warpage of CVD Diamond Wafers using Intermediate Layers for Surface Activated Bonding","authors":"Junsha Wang, T. Suga","doi":"10.23919/ICEP58572.2023.10129652","DOIUrl":"https://doi.org/10.23919/ICEP58572.2023.10129652","url":null,"abstract":"4 inch polycrystalline CVD diamond wafers were bonded to single crystalline oxide wafers by modified surface activated bonding (SAB). To compensate the warpage of diamond wafers, SiO2 was deposited on diamond surface and used as intermediate layers for bonding. Results shows that the warpage and shape of SiO2/diamond wafers influenced the bonded area greatly. For the convex shaped wafer, when the Peak-to-valley (Pv) value was smaller than 4 um, at least 50% of the surface could be bonded; while the Pv exceeded 7 um, the bonding failed. Compared with the saddle shape, convex shaped wafers tended to be bonded easily. Finally, 85% bonded area was achieved. SEM and STEM images demonstrates that the interface was uniformly bonded without any nano-voids.","PeriodicalId":377390,"journal":{"name":"2023 International Conference on Electronics Packaging (ICEP)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129726317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Selective Cu Surface Activation for Cu-Sn Thermocompression Bonding without Flux Deposition 无熔剂沉积Cu- sn热压键合的选择性Cu表面活化
2023 International Conference on Electronics Packaging (ICEP) Pub Date : 2023-04-19 DOI: 10.23919/ICEP58572.2023.10129677
R. Negishi, S. Saito, Itsuro Tomatsu
{"title":"Selective Cu Surface Activation for Cu-Sn Thermocompression Bonding without Flux Deposition","authors":"R. Negishi, S. Saito, Itsuro Tomatsu","doi":"10.23919/ICEP58572.2023.10129677","DOIUrl":"https://doi.org/10.23919/ICEP58572.2023.10129677","url":null,"abstract":"We have developed a Cu selective wet chemical treatment that can deposit an activating compound only on Cu surface. With this treatment, thermocompression bonding (TCB) between Cu and Sn can be performed without applying a flux regent. From the data obtained by changing the compression temperature and time, we assumed that the activating effect of the deposition on Cu was induced by lowering the reaction temperature with Sn. Since the deposition was not observed on other materials including silicon based and organic polymer based dielectrics, we believe this technology is promising to simplify the chip let manufacturing process especially in future high-density interconnection systems.","PeriodicalId":377390,"journal":{"name":"2023 International Conference on Electronics Packaging (ICEP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129369104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Double-sided <111>-oriented nanotwinned copper foils for thermal interface materials in high power electronics 大功率电子热界面材料的双面定向纳米孪晶铜箔
2023 International Conference on Electronics Packaging (ICEP) Pub Date : 2023-04-19 DOI: 10.23919/ICEP58572.2023.10129769
G. Shen, Chih Chen
{"title":"Double-sided <111>-oriented nanotwinned copper foils for thermal interface materials in high power electronics","authors":"G. Shen, Chih Chen","doi":"10.23919/ICEP58572.2023.10129769","DOIUrl":"https://doi.org/10.23919/ICEP58572.2023.10129769","url":null,"abstract":"Double-sided <111>-oriented nanotwinned copper foils with 99% highly <111> orientation and low roughness on both surfaces are fabricated for diffusion bonding. We succeed to use them to bond copper substrates and silicon substrates at 300 °C for 30 min with excellent bonding quality and bonding strength. With the high melting point, thermal conductivity, and bonding strength, the Cu foils show great potential for thermal interface materials in high power electronics.","PeriodicalId":377390,"journal":{"name":"2023 International Conference on Electronics Packaging (ICEP)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127028363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信