Investigation of Solder Resist Opening Uniformity on Flip Chip Substrate

Yuan-Chang Ni, W. Teng, Y. Pai, Carl Chen, Yu-Po Wang
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Abstract

Good solder resist (SR) opening uniformity can effectively avoid electrical defect in the connection between the chip and substrate, including device short, open issue and bump crack issue. The main objective of this research is to propose an optimized process control to improve SR uniformity by controlling queue time through DOE test, including the queue time of tear off PET film after exposure, exposure to development queue time and development chemical renew time. Among them, queue time of tear off PET film after exposure were selected from 1min. to 20min. The exposure to development queue time was set to 1hr to 4hr. The development chemical renew timing was also set. The best SR opening uniformity was revealed by tolerance of opening size, which can be reduced from ±5um to ±3um when queue time of tear off PET film after exposure were set to ≤1min of tear off PET after exposure. The DOE test result sheds light in improving the performance between chip and IC substrate.
倒装芯片衬底上阻焊剂开口均匀性的研究
良好的阻焊性(SR)开孔均匀性可以有效避免芯片与基板连接中的电气缺陷,包括器件短路、开孔问题和磕碰裂纹问题。本研究的主要目的是通过DOE测试控制排队时间,包括PET膜曝光后撕脱排队时间、曝光显影排队时间和显影化学更新时间,提出一种优化的工艺控制,以提高SR均匀性。其中PET胶片曝光后撕脱排队时间为1min。20分钟。暴露于开发队列的时间设置为1到4小时。设定了显影化学更新时间。通过对开口尺寸的公差,可以得到最佳的SR开口均匀性,当PET膜曝光后撕膜排队时间设置为≤1min时,可将PET膜曝光后撕膜排队时间从±5um减小到±3um。DOE测试结果对提高芯片与IC衬底之间的性能具有重要意义。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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