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2012 IEEE Asian Solid State Circuits Conference (A-SSCC)最新文献

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A 101 dB DR 1.1 mW audio delta-sigma modulator with direct-charge-transfer adder and noise shaping enhancement 带有直接电荷转移加法器和噪声整形增强的101 dB DR 1.1 mW音频δ - σ调制器
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522672
Tao Wang, Wei Li, H. Yoshizawa, Mehmet Aslan, G. Temes
{"title":"A 101 dB DR 1.1 mW audio delta-sigma modulator with direct-charge-transfer adder and noise shaping enhancement","authors":"Tao Wang, Wei Li, H. Yoshizawa, Mehmet Aslan, G. Temes","doi":"10.1109/IPEC.2012.6522672","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522672","url":null,"abstract":"A low-power audio delta-sigma modulator (DSM) is presented. Two new techniques are proposed to reduce the overall power dissipation of the modulator: a power-efficient direct-charge-transfer adder is employed, and noise-shaping enhancement is implemented by feeding the differentiated quantization noise to the input of the second integrator. The measured power dissipation is 1.1 mW, the dynamic range is 101.3 dB, the spur-free dynamic range is 112 dB and the signal-to-noise-plus-distortion ratio is 99.3 dB. The power efficiency of this design is among the best in DSMs with high (over 15) ENOBs.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123574609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
On-chip single-inductor dual-output DC-DC boost converter having dual output/input modes for utilizing external power transistor drive and micro-computer controlled MPPT 片上单电感双输出DC-DC升压转换器，具有双输出/输入模式，用于利用外部功率晶体管驱动和微型计算机控制的MPPT
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522614
Y. Nakase, Shin-nosuke Hirose, H. Onoda, Y. Ido, Yoshiaki Shimizu, T. Oishi, T. Kumamoto, Toru Shimizu
{"title":"On-chip single-inductor dual-output DC-DC boost converter having dual output/input modes for utilizing external power transistor drive and micro-computer controlled MPPT","authors":"Y. Nakase, Shin-nosuke Hirose, H. Onoda, Y. Ido, Yoshiaki Shimizu, T. Oishi, T. Kumamoto, Toru Shimizu","doi":"10.1109/IPEC.2012.6522614","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522614","url":null,"abstract":"A compact on-chip SIDO DC-DC converter is proposed for portable equipments operating with a battery or a solar cell. A current up to 30mA is supplied with own transistors in an internal drive mode and more than 100mA by utilizing external power transistors in an external drive mode. The efficiencies are 85% and 84% for each case. A cross regulation problem is solved by inserting an extra cycle before switching the outputs. For solar cell operation, two features are implemented. Any kind of maximum power point tracking MPPT is available by receiving a clock signal calculated by a micro-computer. The converter exploits 99% of the expected maximum power of a solar cell. Backward current protection reduces a leak current by three orders without any performance losses when the light is not available like as in the night.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129495735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A single-inductor dual-output converter with switchable digital-or-analog low-dropout regulator for ripple suppression and high efficiency operation 一种单电感双输出转换器，具有可切换的数字或模拟低差稳压器，用于纹波抑制和高效率运行
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522666
Yu-Huei Lee, Wei-Chung Chen, Chao-Chang Chiu, S. Peng, Kuan-Yu Chu, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Yu-Wen Chen, Chao-Chiun Liang, Chang-An Ho, T. Yu
{"title":"A single-inductor dual-output converter with switchable digital-or-analog low-dropout regulator for ripple suppression and high efficiency operation","authors":"Yu-Huei Lee, Wei-Chung Chen, Chao-Chang Chiu, S. Peng, Kuan-Yu Chu, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Yu-Wen Chen, Chao-Chiun Liang, Chang-An Ho, T. Yu","doi":"10.1109/IPEC.2012.6522666","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522666","url":null,"abstract":"A single-inductor dual-output (SIDO) converter with the switchable digital-or-analog (D/A) low-dropout (LDO) regulator achieves an analog dynamic voltage scaling (ADVS) function for ripple suppression and high efficiency in system-on-a-chip (SoC). The ADVS function helps dynamically adjust the dropout voltage of the switchable D/A LDO regulator with analog operation for ripple suppression according to the load current. On other hand, the switchable D/A LDO regulator activates the digital operation for high efficiency at light loads since the dropout voltage of the LDO regulator can be further reduced. Besides, the bidirectional asynchronous signal pipeline (BASP) can realize the 50nA quiescent current in digital LDO regulator. This chip was fabricated by the 40 nm CMOS process. Experimental results demonstrate the switchable LDO regulator operation with the peak efficiency of 92% and the 7 mV output voltage ripple at 200 mA load because of the ripple suppression. The efficiency can be kept higher than 83% even the load current is 1 mA.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128353856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A spread spectrum clock generator using phase/frequency boosting with a peak power reduction 14.9dB, RMS jitter 1.40ps and power 4.8mW/GHz for USB 3.0 扩频时钟发生器，采用相位/频率增强，峰值功率降低14.9dB, RMS抖动1.40ps, USB 3.0功率4.8mW/GHz
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522681
Seong-Hwan Jeon, Young-Ho Choi, Byungsup Kim, J. Sim, Hong-June Park
{"title":"A spread spectrum clock generator using phase/frequency boosting with a peak power reduction 14.9dB, RMS jitter 1.40ps and power 4.8mW/GHz for USB 3.0","authors":"Seong-Hwan Jeon, Young-Ho Choi, Byungsup Kim, J. Sim, Hong-June Park","doi":"10.1109/IPEC.2012.6522681","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522681","url":null,"abstract":"A 2.5 GHz spread spectrum clock generator (SSCG) is proposed for USB 3.0. The low jitter is achieved by setting the normal loop bandwidth to an optimum value, considering both the VCO noise and the quantization noise of ΔΣ modulator. A large peak power reduction is achieved by maintaining a sharp triangular frequency profile through phase/frequency boosting when the phase error between two inputs of PFD exceeds a limit (2π× 2/9 rad). The peak power reduction and the RMS jitter are measured to be -14.9dB at the RBW of 100 KHz and 1.40ps, respectively. The chip area is 0.34mm × 0.36mm in a 0.13um process.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129351783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Cint-less type-II PLL with ΔΣ DAC based frequency acquisition and reduced quantization noise 无cint ii型锁相环，ΔΣ基于DAC的频率采集和降低量化噪声
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522685
Zhuo Zhang, Xican Chen, W. Rhee, Zhihua Wang
{"title":"A Cint-less type-II PLL with ΔΣ DAC based frequency acquisition and reduced quantization noise","authors":"Zhuo Zhang, Xican Chen, W. Rhee, Zhihua Wang","doi":"10.1109/IPEC.2012.6522685","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522685","url":null,"abstract":"This paper describes a type-II PLL architecture in which a large-area integral-path capacitor (Cint) is replaced with a ΔΣ DAC based frequency acquisition circuit. The proposed voltage-mode acquisition method provides inherent quantization noise suppression by the PLL loop filter. A 1.43-to-2.41GHz Cint-less PLL is implemented in 0.18μm CMOS where the DAC area is <;10% of the total area. The PLL achieves the in-band phase noise of -90dBc/Hz and the reference spur of -55dBc with 500kHz loop bandwidth.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130233003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 20 μV/°C digital offset compensation technique for comparators and differential amplifiers 用于比较器和差分放大器的20 μV/°C数字失调补偿技术
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522625
Koon-Lun Jackie Wong, M. Le, Kwang Young Kim
{"title":"A 20 μV/°C digital offset compensation technique for comparators and differential amplifiers","authors":"Koon-Lun Jackie Wong, M. Le, Kwang Young Kim","doi":"10.1109/IPEC.2012.6522625","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522625","url":null,"abstract":"Digital offset compensation has been widely used for start-up calibration of analog ICs. It can be valuable in the design of an offset control circuit that has a minimal dependence on temperature. This eliminates the need to recalibrate the circuit during normal operation when the temperature may randomly fluctuate. This paper presents a gm-tracking technique used in an offset correction loop that drifts only 20 μV/°C over a temperature range of 0°C to 100°C. Test circuits fabricated in a 40 nm CMOS technology confirm the performance of the proposed technique.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128767447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 5.8GHz digital arbitrary phase-setting Type II PLL in 65nm CMOS with 2.25° Resolution 5.8GHz数字任意相位设置型II型锁相环，65nm CMOS, 2.25°分辨率
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522689
Li Li, M. Flynn, M. Ferriss
{"title":"A 5.8GHz digital arbitrary phase-setting Type II PLL in 65nm CMOS with 2.25° Resolution","authors":"Li Li, M. Flynn, M. Ferriss","doi":"10.1109/IPEC.2012.6522689","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522689","url":null,"abstract":"A fully-integrated 5.8 GHz PLL modulator implemented in 65 nm CMOS achieves digitally-controlled arbitrary phase generation. The PLL consists of a Type II fractional-N PLL with a 1-bit TDC as its PFD. Digital phase setting, which operates by adding a proportional signal to the PFD output, is incorporated in the PLL. The prototype achieves an average phase resolution of 2.25o and a phase range of more than 720o. The entire PLL and output buffer consumes 11 mW.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123225117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S Pipelined-SAR ADC 31.5 fj10b470ms /S管道sar ADC级间增益误差自校正
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522648
Jianyu Zhong, Yan Zhu, Sai-Weng Sin, U. Seng-Pan, R. Martins
{"title":"Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S Pipelined-SAR ADC","authors":"Jianyu Zhong, Yan Zhu, Sai-Weng Sin, U. Seng-Pan, R. Martins","doi":"10.1109/IPEC.2012.6522648","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522648","url":null,"abstract":"This paper proposes an Inter-Stage Gain Error (ISGE) calibration method devoted to correct the residue gain errors induced by the parasitic effects, non-ideal op-amp gain and capacitor mismatch, and also the mismatches for supply-derived reference voltages between two stages for Pipelined-SAR ADC. The calibration reuses the SAR ADC to estimate the overall inter-stage gain error and compensates it in the 2nd-stage DAC in 2 cycles, and it is implemented in a Pipelined-SAR which achieves 10b 470 MS/s in 65 nm CMOS with the FoM of 31.5 fJ/conv.-step by consuming only 6% of the total ADC area (0.049 mm2).","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126203520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Delay-line based fast-locking all-digital pulsewidth-control circuit with programmable duty cycle 基于延迟线的可编程占空比快速锁定全数字脉宽控制电路
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522686
Jun-Ren Su, Te-Wen Liao, C. Hung
{"title":"Delay-line based fast-locking all-digital pulsewidth-control circuit with programmable duty cycle","authors":"Jun-Ren Su, Te-Wen Liao, C. Hung","doi":"10.1109/IPEC.2012.6522686","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522686","url":null,"abstract":"This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty-cycle. In comparison with prior art, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This study presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600MHz, and an input duty cycle ranging from 30 to 70%. It achieves a programmable output duty cycle ranging from 31.25 to 68.75% in increments of 6.25%.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126568256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A (50,2,4) nonbinary LDPC convolutional code decoder chip over GF(256) in 90nm CMOS 基于GF(256)的90nm CMOS(50,2,4)非二进制LDPC卷积码解码器芯片
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522660
Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
{"title":"A (50,2,4) nonbinary LDPC convolutional code decoder chip over GF(256) in 90nm CMOS","authors":"Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/IPEC.2012.6522660","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522660","url":null,"abstract":"A memory-based (ms = 50,dv = 2,dc = 4) nonbinary LDPC convolutional code (NB-LDPC-CC) decoder over GF(256) with layered scheduling is presented. The proposed architecture-aware construction features fewer memory banks, low degree, low period, and better performance. To the best of our knowledge, this is the first architecture discussion and implementation for NB-LDPC-CC decoders. We optimized the architecture of message first-in-first-out (M-FIFO), check node unit, and variable node unit in terms of area and throughput. Jointly designing code and architecture, overall normalized area efficiency can be enhanced by more then six times with respect to decoders of nonbinary LDPC block codes (NB-LDPC BCs). After fabricated in 90nm CMOS, our prototype NB-LDPC-CC decoder chip can achieve maximum throughput of 22.8Mbps with frequency of 285MHz. The measured average power is 211mW at a typical operating voltage of 1.0V.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121651375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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