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A 3.0-W wireless power receiver circuit with 75-% overall efficiency 一个总效率为75%的3.0 w无线电源接收器电路
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522636
Young-Jin Moon, Yong-seong Roh, C. Yoo, Dong-Zo Kim
{"title":"A 3.0-W wireless power receiver circuit with 75-% overall efficiency","authors":"Young-Jin Moon, Yong-seong Roh, C. Yoo, Dong-Zo Kim","doi":"10.1109/IPEC.2012.6522636","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522636","url":null,"abstract":"Resonant magnetic coupling is utilized to transfer 3.0-W power without wire. The received AC power is rectified by an active rectifier and then converted to the desired DC level by a switching DC-DC converter. The reverse leakage of the active rectifier is prevented by a delay locked loop (DLL) based delay compensation circuit. The overall power efficiency of the wireless power receiver implemented in a 0.35-μm BCDMOS technology is 75-% when the resonant frequency of the magnetic resonator is 3.23-MHz.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121818665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
An energy-efficient 2.4-GHz PSK/16-QAM transmitter 节能2.4 ghz PSK/16-QAM发射机
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/ASSCC.2012.6570802
Chun-Yu Lin, Yao-Hong Liu, C. Fu, H. Lakdawala, Tsung-Hsien Lin
{"title":"An energy-efficient 2.4-GHz PSK/16-QAM transmitter","authors":"Chun-Yu Lin, Yao-Hong Liu, C. Fu, H. Lakdawala, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2012.6570802","DOIUrl":"https://doi.org/10.1109/ASSCC.2012.6570802","url":null,"abstract":"A 2.4-GHz energy-efficient transmitter (TX) which supports multiple modulation schemes is reported. The proposed TX is based on the phase-selector architecture, where the modulation signal is generated by interpolating among quadrature phases at RF. This TX demonstrates the capability of supporting various PSK (OQPSK, HS-OQPSK, and 8-PSK) and the 16-QAM modulations. Fabricated in a 90-nm CMOS process, the TX consumes 8.9 mW and 13.8 mW at PSK and QAM modes, respectively. The maximum data rate is 105 Mbps under -3 dBm output power and 10.6 % EVM.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"1933 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128779151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Automatic loading detection (ALD) technique for 92% high efficiency interleaving power factor correction (PFC) over a wide output power of 180W 自动负载检测(ALD)技术，在180W的宽输出功率下实现92%的高效率交错功率因数校正(PFC)
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522667
Jen-Chive Tsai, Chun-Yen Chen, Yi-Ting Chen, Chia-Lung Ni, Yi-Ping Su, Ke-Horng Chen, Yu-Wen Chen, Chao-Chiun Liang, Chang-An Ho, T. Yu
{"title":"Automatic loading detection (ALD) technique for 92% high efficiency interleaving power factor correction (PFC) over a wide output power of 180W","authors":"Jen-Chive Tsai, Chun-Yen Chen, Yi-Ting Chen, Chia-Lung Ni, Yi-Ping Su, Ke-Horng Chen, Yu-Wen Chen, Chao-Chiun Liang, Chang-An Ho, T. Yu","doi":"10.1109/IPEC.2012.6522667","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522667","url":null,"abstract":"The proposed automatic loading detection (ALD) technique keeps high efficiency in interleaving power factor correction (PFC) over a wide load range. With the advantages of small input/output filter and output ripple in the interleaving mechanism, the improved efficiency by the ALD technique at light loads due to reduced switching loss can be widely used in the adapter of portable electronics. The ALD technique can calculate the power by the detection of peak input voltage to reduce the switching loss since the slave channel can be completely turned off for power saving at light loads. Therefore, the boundary control mode (BCM) control can simultaneously provide high power and keep high conversion efficiency both at light and heavy loads. The highly integrated PFC controller fabricated in TSMC 800V UHV process shows high efficiency of 92% over a wide output power of 180 W.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130635760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.5-V 5.5-GHz class-C-VCO-based PLL with ultra-low-power ILFO in 65 nm CMOS 一种基于0.5 v 5.5 ghz c - vco的锁相环，在65纳米CMOS中具有超低功耗ILFO
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/ASSCC.2012.6570785
S. Ikeda, T. Kamimura, Sang-yeop Lee, Norifumi Kanemaru, Hiroyuki Ito, N. Ishihara, K. Masu
{"title":"A 0.5-V 5.5-GHz class-C-VCO-based PLL with ultra-low-power ILFO in 65 nm CMOS","authors":"S. Ikeda, T. Kamimura, Sang-yeop Lee, Norifumi Kanemaru, Hiroyuki Ito, N. Ishihara, K. Masu","doi":"10.1109/ASSCC.2012.6570785","DOIUrl":"https://doi.org/10.1109/ASSCC.2012.6570785","url":null,"abstract":"In this paper, an ultra-low-power 5.5-GHz PLL is proposed which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO for operation under a power supply of 0.5 V. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The proposed PLL was fabricated in 65nm CMOS. The whole circuit consumes 1.6 mW under the power supply of 0.5V. With a 34.6-MHz reference, it shows a 1-MHz-offset phase noise of -105 dBc/Hz and a reference spur level lower than -65dBc at 5.5 GHz.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131434815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 60 GHz wideband active balun using magnitude and phase concurrent correction technique in 65nm CMOS 一种采用幅度相位同步校正技术的60 GHz宽带有源平衡器
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522678
S. Chou, Fu-Chien Huang, Chorng-Kuang Wang
{"title":"A 60 GHz wideband active balun using magnitude and phase concurrent correction technique in 65nm CMOS","authors":"S. Chou, Fu-Chien Huang, Chorng-Kuang Wang","doi":"10.1109/IPEC.2012.6522678","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522678","url":null,"abstract":"A wideband magnitude and phase concurrent correction technique (MPCCT) is proposed in this paper. The MPCCT can concurrently correct the gain and phase imbalances between the differential signals of an active balun. This technique employs positive feedback and negative feedback as correction circuits. The two feedback loops redistribute the gain and phase imbalances into the differential outputs equally. The balun using MPCCT has the measured maximum gain 6.1dB at 59 GHz while the gain and phase imbalances are 0.14 dB and 0.7° respectively. The bandwidth of the balun is 12 GHz. The measured results demonstrate the robust correction at millimeter-wave (MMW) frequency. The power consumption is 11.6mW with 1V supply voltage and the chip area is 0.26 mm2 excluding the pads.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132347107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A dynamic resource controller with network-on-chip for a 10.5nJ/pixel object recognition processor 用于10.5nJ/像素目标识别处理器的动态资源控制器
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522663
Jinwook Oh, Injoon Hong, Gyeonghoon Kim, Junyoung Park, H. Yoo
{"title":"A dynamic resource controller with network-on-chip for a 10.5nJ/pixel object recognition processor","authors":"Jinwook Oh, Injoon Hong, Gyeonghoon Kim, Junyoung Park, H. Yoo","doi":"10.1109/IPEC.2012.6522663","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522663","url":null,"abstract":"This paper presents a dynamic resource controller (DRC) with network-on-chip (NoC) for an energy-efficient multi-core processor. A total 21 cores in 5 local voltage/frequency islands (VFIs) can be controlled by dynamic resource management (DRM) with the proposed workload-utilization product based prediction model. And a 0.31mm2 compact 8×8 NoC switch is designed to reduce unnecessary ~24% power dissipation of each VFI by adopting DVFS and the bandwidth regulation. As a result, thanks to 42% reduction of power-delay product by DRM-based NoC architecture, the 32 mm2 multi-core processor, fabricated 0.13μm CMOS process, achieves 10.5nJ/pixel efficiency, 3.54x improvement compared to state-of-the-art object recognition processors.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132563230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 22.4 μW 80dB SNDR ΣΔ modulator with passive analog adder and SAR quantizer for EMG application 一个22.4 μW 80dB SNDR ΣΔ调制器，带无源模拟加成器和SAR量化器
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522674
Zhijie Chen, Yang Jiang, Chen-Yan Cai, Hegong Wei, Sai-Weng Sin, U. Seng-Pan, Zhihua Wang, R. Martins
{"title":"A 22.4 μW 80dB SNDR ΣΔ modulator with passive analog adder and SAR quantizer for EMG application","authors":"Zhijie Chen, Yang Jiang, Chen-Yan Cai, Hegong Wei, Sai-Weng Sin, U. Seng-Pan, Zhihua Wang, R. Martins","doi":"10.1109/IPEC.2012.6522674","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522674","url":null,"abstract":"A Feed-Forward (FF) multi-bit ΣΔ modulator with passive analog adder and 4-bit Successive Approximation (SA) quantizer is presented. The modulator covers the 10KHz bandwidth according to electromyography application. The design utilizes the same DAC array of the SAR quantizer to realize analog summation for the FF signal, which significantly reduces the power dissipation and the silicon area. The modulator operates at 1MS/s with IV supply. The prototype chip implemented in 65nm CMOS achieves 80dB SNDR and 81dB DR with 22.4μW power consumption. The Figure of Merit (FoM) is 0.13 pJ/conv.-step.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126591250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
The 3.0GHz 64-thread SPARC T4 processor 3.0GHz 64线程SPARC T4处理器
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522613
Jinuk Luke Shin, R. Golla, H. Li, Sudesna Dash, M. Doherty, G. Grohoski, C. McAllister
{"title":"The 3.0GHz 64-thread SPARC T4 processor","authors":"Jinuk Luke Shin, R. Golla, H. Li, Sudesna Dash, M. Doherty, G. Grohoski, C. McAllister","doi":"10.1109/IPEC.2012.6522613","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522613","url":null,"abstract":"The SPARC T4 processor introduces the next generation multi-threaded S3 core and delivers a significant single-thread performance improvement over its predecessor. The chip integrates eight S3 cores, an 8-Bank 4MB L3 Cache, a 768GB/sec crossbar, a memory controller, PCI Gen2.0, 10G Ethernet and a cache coherency controller with 2.4Tb/s highspeed I/Os. The dual-issue, out-of-order execution core features a 16-stage integer pipeline, extensive branch predictions, dynamic threading and an enhanced cryptographic processing unit. The 406mm2 die is fabricated in TSMC's 40nm process and contains 855million transistors and 2.6million flip-flops in a flipchip ceramic package. Enhanced physical design methodologies and extensive power management features enable 3.0GHz operation in the same power envelope of its predecessor.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130738679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An asymmetrical QPSK/OOK transceiver SoC and 15:1 JPEG encoder IC for multifunction wireless capsule endoscopy 用于多功能无线胶囊内窥镜的非对称QPSK/OOK收发器SoC和15:1 JPEG编码器IC
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522695
Yuan Gao, San-Jeow Cheng, Wei-Da Toh, Y. Kwok, K.-C. B. Tan, Xi Chen, W. Mok, H. Win, Bin Zhao, Shengxi Diao, Cabuk Alper, Yuanjin Zheng, Sumei Sun, M. Je, C. Heng
{"title":"An asymmetrical QPSK/OOK transceiver SoC and 15:1 JPEG encoder IC for multifunction wireless capsule endoscopy","authors":"Yuan Gao, San-Jeow Cheng, Wei-Da Toh, Y. Kwok, K.-C. B. Tan, Xi Chen, W. Mok, H. Win, Bin Zhao, Shengxi Diao, Cabuk Alper, Yuanjin Zheng, Sumei Sun, M. Je, C. Heng","doi":"10.1109/IPEC.2012.6522695","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522695","url":null,"abstract":"A chipset including a low power asymmetrical QPSK/OOK transceiver SoC and a 15:1 JPEG image encoder IC is presented for wireless capsule endoscopy. The proposed asymmetrical bi-directional telemetry link supports high-data-rate image transmission with QPSK modulation and low-data-rate actuator control data reception with OOK modulation. To transmit high-quality images with high spectral efficiency, a low power JPEG encoder with compression ratio as high as 15:1 is employed to compress raw image data with subsampling technique in YUV color plane. Implemented in 0.18-μm CMOS, the QPSK TX consumes 5 mW at -6 dBm of output power with 3Mb/s data rate while the OOK RX achieves -60 dBm of sensitivity at 500-kb/s data rate with 6-mW power consumption. A prototype capsule system has been implemented for wireless endoscopy using the developed chipset. With duty cycling, the average power consumption of TX is 2.5 mW when transmitting at 3-fps frame rate.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133149754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Expectations for the semiconductor technologies in EVs and HVs 对电动汽车和高压汽车半导体技术的期望
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522618
S. Sasaki
{"title":"Expectations for the semiconductor technologies in EVs and HVs","authors":"S. Sasaki","doi":"10.1109/IPEC.2012.6522618","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522618","url":null,"abstract":"EVs and HVs will have a certain share in the future market place. To populate these vehicles, the semiconductor technologies will play a central role. And those technologies will be crucial for the quality of EVs and HVs. To populate EV and HVs, cost will be the most critical factor even in the future. The portion of battery cost will still be large compared to inverter and motor cost. Therefore there is a need of cutting the cost of batteries for EVs and HVs. To do so, there are some technologies undergoing. These technologies are presented and expectations for the semiconductor technologies are explained.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"15 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126580885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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