A Cint-less type-II PLL with ΔΣ DAC based frequency acquisition and reduced quantization noise

Abstract

This paper describes a type-II PLL architecture in which a large-area integral-path capacitor (Cint) is replaced with a ΔΣ DAC based frequency acquisition circuit. The proposed voltage-mode acquisition method provides inherent quantization noise suppression by the PLL loop filter. A 1.43-to-2.41GHz Cint-less PLL is implemented in 0.18μm CMOS where the DAC area is <;10% of the total area. The PLL achieves the in-band phase noise of -90dBc/Hz and the reference spur of -55dBc with 500kHz loop bandwidth.