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2012 IEEE Asian Solid State Circuits Conference (A-SSCC)最新文献

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A 7.5mW 9MHz CT ΔΣ modulator in 65nm CMOS with 69 dB SNDR and reduced sensitivity to loop delay variations 7.5mW 9MHz CT ΔΣ调制器，65nm CMOS, SNDR 69 dB，降低了对环路延迟变化的灵敏度
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522671
Mattias Andersson, Martin Anderson, L. Sundstrom, P. Andreani
{"title":"A 7.5mW 9MHz CT ΔΣ modulator in 65nm CMOS with 69 dB SNDR and reduced sensitivity to loop delay variations","authors":"Mattias Andersson, Martin Anderson, L. Sundstrom, P. Andreani","doi":"10.1109/IPEC.2012.6522671","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522671","url":null,"abstract":"This paper presents a 3rd-order, 3-bit continuous-time (CT) ΔΣ modulator for an LTE radio receiver. By adopting a return-to-zero (RZ) pulse in the innermost DAC, the modulator shows a reduced sensitivity to loop-delay variations, and the additional loop delay compensation usually needed in CT modulators can be omitted. The modulator has been implemented in a 65 nm CMOS process, where it occupies an area of 0.2 mm × 0.4 mm. It achieves an SNR of 71 dB and an SNDR of 69 dB over a 9 MHz bandwidth with an oversampling ratio of 16, while consuming 7.5 mW from a 1.2 V supply.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121480151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 0.05mm2 0.6V 500kS/s 14.3fJ/conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager 用于三维堆叠CMOS成像仪的0.05mm2 0.6V 500kS/s 14.3fJ/转换步11位两步切换SAR ADC
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522651
Jin-Yi Lin, Hsin-Yuan Huang, C. Hsieh, Hung-I Chen
{"title":"A 0.05mm2 0.6V 500kS/s 14.3fJ/conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager","authors":"Jin-Yi Lin, Hsin-Yuan Huang, C. Hsieh, Hung-I Chen","doi":"10.1109/IPEC.2012.6522651","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522651","url":null,"abstract":"This paper proposes a two-step switching SAR ADC architecture that greatly reduces the area and power consumption of the DAC network. The total number of unit capacitors of the proposed approach is only 64C. In addition, to reduce meta-stability at low-supply operation, a supply-boost technique of comparator is also employed. The prototype chip realized an 11-bit SAR ADC in a 0.18μm CMOS technology with an extremely small core area of 0.05mm2. With a single 0.6V supply voltage, the prototype consumes 5.02uW at 500kS/s, and achieves an ENOB of 9.45bit and a FoM of 14.34fJ/conversion-step, respectively.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"210 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An integrated variable positive/negative temperature coefficient read reference generator for MLC PCM/NAND Hybrid 3D SSD 一种用于MLC PCM/NAND混合3D固态硬盘的集成可变正/负温度系数读取参考发生器
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522688
K. Miyaji, K. Johguchi, K. Higuchi, K. Takeuchi
{"title":"An integrated variable positive/negative temperature coefficient read reference generator for MLC PCM/NAND Hybrid 3D SSD","authors":"K. Miyaji, K. Johguchi, K. Higuchi, K. Takeuchi","doi":"10.1109/IPEC.2012.6522688","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522688","url":null,"abstract":"An integrated variable temperature coefficient (TC) reference generator for multi-level cell phase change memory (PCM)/NAND flash memory hybrid three dimensional solidstate drive is proposed and demonstrated by 0.18μm CMOS process. The proposed generator outputs both positive and negative TC reference current and voltage for PCM and NAND, respectively. TC is programmable and it can be widely changed down to -5.47mV/K and up to 5.74mV/K. Output level is also variable and it is independently controlled from the TC control. The flexible TC and output level control also enable a compensation of characteristics changes due to the program/erase cycling as wells as the process variations of the memory devices. The size of the reference generator is 0.195mm2. The power consumption is 0.68mW at 120degC, 2.3V output.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131537646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.38 mm2, 10mhz-6.6 GHz quadrature frequency synthesizer using fractional-N injection-locked technique 0.38 mm2, 10mhz-6.6 GHz正交频率合成器，采用分数- n注入锁定技术
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/ASSCC.2012.6570787
W. Deng, A. Musa, K. Okada, A. Matsuzawa
{"title":"A 0.38 mm2, 10mhz-6.6 GHz quadrature frequency synthesizer using fractional-N injection-locked technique","authors":"W. Deng, A. Musa, K. Okada, A. Matsuzawa","doi":"10.1109/ASSCC.2012.6570787","DOIUrl":"https://doi.org/10.1109/ASSCC.2012.6570787","url":null,"abstract":"This paper presents an area- and power-efficient delta-sigma frequency synthesizer with a quadrature phase output using a fractional-N injection-locking technique. A digital calibration scheme is proposed to compensate for the PVT variations. Implemented in a 65nm CMOS process, this work demonstrates 10 MHz to 6.6 GHz continuous frequency coverage with quadrature output, while only occupies a small area of 0.38 mm2 and consumes 16-26 mW depending on output frequency. The normalized phase noise achieves -135.3 dBc/Hz at 3 MHz offset, and -95.1 dBc/Hz in-band phase noise at 10 kHz offset, from a 1.7GHz carrier frequency.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131893145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system 具有超低功耗片上电荷回收电源电路和系统的绿色半导体技术
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522638
Kazuhiro Ueda, Okura Shunsuke, F. Morishita, K. Arimoto, Leona Okamura, T. Yoshihara
{"title":"Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system","authors":"Kazuhiro Ueda, Okura Shunsuke, F. Morishita, K. Arimoto, Leona Okamura, T. Yoshihara","doi":"10.1109/IPEC.2012.6522638","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522638","url":null,"abstract":"For low power consumption which makes more than doubles a battery life, the charge-recycling system by reuse the energy between the two or more CPUs and the task scheduling technique for high efficiency are proposed. In this architecture, CPUs are divided into upper and lower load groups, and electrical charges are shared among the stacked CPUs and a tank capacitor. To control divided loads, a high speed and efficient regulator are needed. The internal circuit voltage variation between upper and lower modules is solved by seven LDO regulators, boosting switched capacitor and the tank capacitor. As a result, the stable voltage can be supplied to each CPU, even if upper and lower loads are different or battery is used. The LDOs improve the margin of accumulation of tank capacitor or task schedule operation, and the power efficiency is raised further. The system can be on-chip without external large control circuit and inductor like switching regulator. The test chips were fabricated using 90nm standard CMOS technology. Although the power efficiency of the conventional system with a simple LDO is 44.4% at the maximum, that of the proposed charge-recycling system improves to 88.9%.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134433272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1.2V 64fJ/conversion-step continuous-time ΣΔ modulator using asynchronous SAR quantizer and digital ΣΔ truncator 采用异步SAR量化器和数字ΣΔ截断器的1.2V 64fJ/转换步长连续时间ΣΔ调制器
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522670
Hung-Chieh Tsai, Chilun Lo, Chen-Yen Ho, Yu-Hsin Lin
{"title":"A 1.2V 64fJ/conversion-step continuous-time ΣΔ modulator using asynchronous SAR quantizer and digital ΣΔ truncator","authors":"Hung-Chieh Tsai, Chilun Lo, Chen-Yen Ho, Yu-Hsin Lin","doi":"10.1109/IPEC.2012.6522670","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522670","url":null,"abstract":"A 3rd-order single-loop continuous time sigma-delta modulator (CTSDM) with 6-bit asynchronous SAR quantizer and digital delta-sigma truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed asynchronous SAR based quantizer reduces the area and power dramatically with the help of digital truncation technique. In addition, the modulator incorporating the proposed operational amplifiers (op-amp) with ac coupled push-pull stage is to improve the high frequency driving capability. The modulator sampling at 65MHz achieves 83.4dB dynamic range (DR) and 80/79.6dB peak SNR/SNDR with 1.92MHz bandwidth (BW) in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Implemented in 40nm CMOS, the modulator occupies 0.051mm2 and consumes 1.91mW from a 1.2V supply. A 64fJ/conversion figure of merit (FOM) is achieved.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133485550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 45μW injection-locked FSK Wake-Up receiver for crystal-less wireless body-area-network 用于无晶无线体域网络的45μW注入锁定FSK唤醒接收器
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522693
Joonsung Bae, H. Yoo
{"title":"A 45μW injection-locked FSK Wake-Up receiver for crystal-less wireless body-area-network","authors":"Joonsung Bae, H. Yoo","doi":"10.1109/IPEC.2012.6522693","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522693","url":null,"abstract":"A dedicated ultra-low power fully integrated FSK wake-up receiver (WuRx) for wireless body area network (WBAN) is implemented in 0.18μm CMOS technology with 0.7V supply. An injection-locking digitally-controlled oscillator (ILDCO) enables power-efficient front end amplification, and autocalibration of DCO by successive approximation resister (SAR) algorithm. The fabricated 1mm2 single chip WuRx consumes 45μW with a data rate of 312kb/s, providing an 80MHz reference frequency with 0.25% stability to the main transceiver for crystal-less WBAN sensor nodes.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"14 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133044432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 1.94mm2, 38.17mW dual VP8/H.264 Full-HD encoder/decoder LSI for Social Network Services (SNS) over smart-phones 1.94mm2, 38.17mW双VP8/H.264用于智能手机社交网络服务(SNS)的全高清编码器/解码器LSI
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522611
Chi-Cheng Ju, Tsu-Ming Liu, Yi-Hau Chen, Kun-Bin Lee, Chia-Yun Cheng, Hsueh-Te Chao, Chih-Ming Wang, Tung-Hsing Wu, Ting-An Lin, Han-Liang Chou, Yu-Kun Lin, C. Liu, Wei-Cing Li, Yi-Hsin Huang, Tsung-Chuan Ma, Chun-Chia Chen, Hue-Min Lin, Min-Hao Chiu, Sheng-Jen Wang, Yung-Chang Chang, Chung-Hung Tsai
{"title":"A 1.94mm2, 38.17mW dual VP8/H.264 Full-HD encoder/decoder LSI for Social Network Services (SNS) over smart-phones","authors":"Chi-Cheng Ju, Tsu-Ming Liu, Yi-Hau Chen, Kun-Bin Lee, Chia-Yun Cheng, Hsueh-Te Chao, Chih-Ming Wang, Tung-Hsing Wu, Ting-An Lin, Han-Liang Chou, Yu-Kun Lin, C. Liu, Wei-Cing Li, Yi-Hsin Huang, Tsung-Chuan Ma, Chun-Chia Chen, Hue-Min Lin, Min-Hao Chiu, Sheng-Jen Wang, Yung-Chang Chang, Chung-Hung Tsai","doi":"10.1109/IPEC.2012.6522611","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522611","url":null,"abstract":"A first dual-standard video encoder and decoder LSI providing VP8 (i.e. video format of WebM project for use of web's video) or H.264/AVC video recording and playback simultaneously is implemented with 28nm CMOS and occupies 1.94mm2 of core area. Several area-efficient techniques are realized, leading to 43.6% of area reduction. A new rate control is designed to facilitate the adaptation of video data and frame rates for network services. Two fast algorithms and new bool encoder/decoder are proposed to enhance power efficiency. This chip consumes 28.15mW and 10.02mW of VP8 encoder and decoder average power for 1080p@30fps at 0.9V, respectively.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129052480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 60GHz CMOS rectifier with −27.5dBm sensitivity for mm-Wave power detection 60GHz CMOS整流器，−27.5dBm灵敏度，用于毫米波功率检测
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522680
S. Kawai, T. Mitomo, S. Saigusa
{"title":"A 60GHz CMOS rectifier with −27.5dBm sensitivity for mm-Wave power detection","authors":"S. Kawai, T. Mitomo, S. Saigusa","doi":"10.1109/IPEC.2012.6522680","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522680","url":null,"abstract":"A CMOS rectifier that converts 60 GHz signal to DC voltage is presented for millimeter-Wave (mm-Wave) power detection. The sensitivity of the rectifier is -27.5 dBm, which is 22 dB higher than in the previous work. The optimization method for the rectifier is proposed considering the power matching design and loss of the passive devices at 60GHz. According to the proposed method, the number of stage should be decreased because the stacked structure that is often used at frequency of several GHz doesn't increase the sensitivity in the case of 60GHz. The loss of the passive devices is minimized by adopting the proposed optimization method.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131056910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A package bondwire based 80% efficiency 80MHz fully-integrated buck converter with precise DCM operation and enhanced light-load efficiency 基于封装键合线的80%效率80MHz全集成降压转换器，具有精确的DCM操作和增强的轻负载效率
2012 IEEE Asian Solid State Circuits Conference (A-SSCC) Pub Date : 2012-12-01 DOI: 10.1109/IPEC.2012.6522665
Cheng Huang, K. Mok
{"title":"A package bondwire based 80% efficiency 80MHz fully-integrated buck converter with precise DCM operation and enhanced light-load efficiency","authors":"Cheng Huang, K. Mok","doi":"10.1109/IPEC.2012.6522665","DOIUrl":"https://doi.org/10.1109/IPEC.2012.6522665","url":null,"abstract":"An 80MHz fixed frequency PWM fully-integrated area-efficient buck converter utilizing standard package bondwire as power inductor with enhanced light-load efficiency is presented which occupies 1.2mm2 in 0.13μm CMOS. Package bondwire instead of on-chip spiral metal or special spiral bondwire is utilized as power inductor. Two negative feedback loops are proposed as NMOS gate-drive controller to introduce Adaptive Dead-Time (ADT) and precise DiscontinuousConduction-Mode (DCM) operation with self-eliminated reverse current at high frequency, which frees the accuracy requirement of the package bondwire inductor and boosts up the light-load efficiency over 72% at 10mA while reaches 80% at 270mA with a 6.7nH inductor. 8 times efficiency improvement at 10mA is observed comparing to the situation with all the proposed function disabled. Converters with different package bondwire inductors from 3nH to 10nH are tested to verify the robustness.","PeriodicalId":367288,"journal":{"name":"2012 IEEE Asian Solid State Circuits Conference (A-SSCC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127534403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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