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Microprogramming instruction systolic arrays 微程序指令收缩数组
MICRO 22 Pub Date : 1989-08-01 DOI: 10.1145/75362.75402
P. Lenders, Heiko Schröder, P. Strazdins
{"title":"Microprogramming instruction systolic arrays","authors":"P. Lenders, Heiko Schröder, P. Strazdins","doi":"10.1145/75362.75402","DOIUrl":"https://doi.org/10.1145/75362.75402","url":null,"abstract":"The instruction systolic array (ISA) is a programmable parallel architecture suitable for VLSI implementation. This paper presents a generalization of the ISA, called the microprogrammed ISA, which uses simple microprogramming techniques. Microprogrammed ISAs use dynamic microcodes whose length and contents are tailor made to the current program to be executed, and this can be efficiently implemented in VLSI. Here, microprogramming has the novel advantage of extending the range of algorithms that can be implemented on a given ISA. In particular, microprogramming can extend an ISA's effective communication abilities. Also, the reduction of the program input bandwidth (and pinout) afforded by microprogramming is even more important on large-scale MIMD architectures, such as the ISA. This paper also presents a weakest precondition semantics for the (microprogrammed) ISA model, which provides a means for verifying microprogrammed ISA programs. The semantics is modeled at the micro level, and has potential in the optimization of the microcodes of ISA programs.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115402776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Microarchitecture choices (implementation of the VAX) 微架构选择(VAX的实现)
MICRO 22 Pub Date : 1989-08-01 DOI: 10.1145/75362.75421
Y. Patt
{"title":"Microarchitecture choices (implementation of the VAX)","authors":"Y. Patt","doi":"10.1145/75362.75421","DOIUrl":"https://doi.org/10.1145/75362.75421","url":null,"abstract":"The VAX Architecture provides hardware implementors with an opportunity or a nightmare, depending on your point of view. Such characteristics as 304 opcodes, a large number of addressing modes, a large number of supported data types, and non-regularities in the ISA semantics all provide challenges to the microarchitect. The VAX architecture was introduced in 1977 with its first microarchitecture, the VAX 11/780, a TTL MSI implementation. Since then, there have been several distinct implementations, each reflecting (1) the technology in which it was implemented, (2) the performance/cost tradeoffs it was supposed to consider, and (3) the design methodology of its implementors. This paper is a first attempt at discussing several VAX implementations from the standpoint of the choices made in the microarchitecture as driven by the context of the device technology, the performance/cost tradeoffs, and other considerations.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122532827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cost-effective design of application specific VLIW processors using the SCARCE framework 使用稀缺框架的应用程序专用VLIW处理器的经济高效设计
MICRO 22 Pub Date : 1989-08-01 DOI: 10.1145/75362.75400
Hans M. Mulder, Robert J. Portier
{"title":"Cost-effective design of application specific VLIW processors using the SCARCE framework","authors":"Hans M. Mulder, Robert J. Portier","doi":"10.1145/75362.75400","DOIUrl":"https://doi.org/10.1145/75362.75400","url":null,"abstract":"Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs; especially in the case of low-volume productions. The flexibility of horizontal-microcoded machines allows these costs to be reduced, but the flexibility often reduces efficiency. VLIW is a new and promising concept for the design of low-cost, high-performance parallel computer systems. We suggest that the VLIW concept can also be used as a basis for cost-effective design of application-specific processors which must exploit application-resident parallelism.\u0000The SCARCE (SCalable ARChitecture Experiment) framework, an approach for cost-effective design of application-specific processors, provides features which allow the design of retargetable VLIW architectures. However, a retargetable VLIW architecture is only effective if there is a retargetable VLIW compiler. Since a VLIW compiler is an essential part of the VLIW architecture, tradeoffs must be made between the variety of VLIW architectures and the compiler complexity. We suggest that limiting the flexibility of the retargetable VLIW architecture does not necessary reduce the application space.\u0000This paper discusses the issues related to the design of a retargetable VLIW processor architecture and compiler within the SCARCE framework.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"145 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128610506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A computing unit for FFP function evaluation in support of correctness proofs 支持正确性证明的FFP函数计算单元
MICRO 22 Pub Date : 1989-08-01 DOI: 10.1145/75362.75426
M. Alderighi, G. Sechi, R. Vaccaro, L. Verdoscia
{"title":"A computing unit for FFP function evaluation in support of correctness proofs","authors":"M. Alderighi, G. Sechi, R. Vaccaro, L. Verdoscia","doi":"10.1145/75362.75426","DOIUrl":"https://doi.org/10.1145/75362.75426","url":null,"abstract":"Constructing such systerns calls for powerful theoretical apparatus and technological tools to specify and implement all their different and numerous functions. Moreover, effective design methods are needed to ensure the strength of the final systems. Finally dedicated programming languages are required for the formal specification of complex operations, such as programs. Unfortunately operating complexity impairs:","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123487292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A functional model of clocked microarchitectures 时钟微架构的功能模型
MICRO 22 Pub Date : 1989-08-01 DOI: 10.1145/75362.75420
C. Charlton, D. Jackson, P. Leng
{"title":"A functional model of clocked microarchitectures","authors":"C. Charlton, D. Jackson, P. Leng","doi":"10.1145/75362.75420","DOIUrl":"https://doi.org/10.1145/75362.75420","url":null,"abstract":"Models for the simulation of computer systems at the microarchitectural level are widely used to assist in design analysis and verification, and the development of microcode. The general model we describe here represents the behaviour of a clocked microarchitecture through the application of functions to component states and signal values. The operational semantics of the model are based partly on data flow and partly on graph reduction, allowing use to be made of the concept of 'lazy' evaluation to aid efficient simulation.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115561120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Functional languages in microcode compilers 微码编译器中的函数式语言
MICRO 22 Pub Date : 1989-08-01 DOI: 10.1145/75362.75397
S. J. Allan
{"title":"Functional languages in microcode compilers","authors":"S. J. Allan","doi":"10.1145/75362.75397","DOIUrl":"https://doi.org/10.1145/75362.75397","url":null,"abstract":"This paper discusses the advantages of using high-level languages in the development of microcode. It also describes reasons functional programming languages should be considered as the source language for microcode compilers. The emergence of parallel execution in microarchitectures dictates that parallelism must be extracted from the microcode programs. This paper shows how functional languages meet the needs of microprogrammers by allowing them to express their algorithms in natural ways while allowing the microcode compiler to extract the parallelism from the program.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114791634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Peephole optimization as a targeting and coupling tool 作为目标和耦合工具的窥视孔优化
MICRO 22 Pub Date : 1989-08-01 DOI: 10.1145/75362.75407
V. Allan
{"title":"Peephole optimization as a targeting and coupling tool","authors":"V. Allan","doi":"10.1145/75362.75407","DOIUrl":"https://doi.org/10.1145/75362.75407","url":null,"abstract":"The term peephole optimization is used to mean the pattern matching and conditional replacement performed on small sections of the intermediate form.\u0000The circular dependence between the code generation phases implies that local optimals are rarely global optimals. There are several reactions: (1) accept the local optimal, (2) develop intermediate goals whose achievement suggest global optimality, (3) retain the choices so that the decisions can be made later, (4) optimize the object code by replacing awkward or overly constrained segments of code with improved ones. Optimizing the object code has several advantages. First, code generation is greatly simplified. The code generator is allowed to forgo case analysis and utilize only a subset of the machine's instructions and addressing modes [BD88,DF84a,DF84b,DF87]. Second, a phase ordering problem often encountered in optimizations is reduced.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123355326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multiple operation memory structures 多操作存储器结构
MICRO 22 Pub Date : 1989-08-01 DOI: 10.1145/75362.75417
M. C. Ertem
{"title":"Multiple operation memory structures","authors":"M. C. Ertem","doi":"10.1145/75362.75417","DOIUrl":"https://doi.org/10.1145/75362.75417","url":null,"abstract":"This paper describes architectures based on a new memory structure. Memory systems which can perform multiple transfers are described and issues in processor architecture are considered. A general model for memory operations is given, and the classical single transfer memory structures are described. Based on the generalized model, new structures which allow multiple transfers to be performed as a single processor operation are developed. Some architectural considerations at the processor level to support these kinds of memory systems are then discussed. The advantages and disadvantages of these new structures as compared to conventional memories are also discussed and a preliminary performance evaluation is done. This discussion generally refers to the random access, physical, main memory in the system, although many of the results are applicable to other storage devices.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130180495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VLSI based microprogramming evaluation system to support an instructional laboratory 基于VLSI的教学实验室微程序评估系统
MICRO 22 Pub Date : 1989-08-01 DOI: 10.1145/75362.75413
A. Parker, J. O. Hamblen
{"title":"A VLSI based microprogramming evaluation system to support an instructional laboratory","authors":"A. Parker, J. O. Hamblen","doi":"10.1145/75362.75413","DOIUrl":"https://doi.org/10.1145/75362.75413","url":null,"abstract":"A new low-cost VLSI based microprogrammable computer system is described. This system is an ideal candidate for use in student microprogramming laboratories. The authors describe their experiences in using this computer.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132920680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ASIC microprocessors ASIC微处理器
MICRO 22 Pub Date : 1989-08-01 DOI: 10.1145/75362.75425
M. Flynn, R. I. Winner
{"title":"ASIC microprocessors","authors":"M. Flynn, R. I. Winner","doi":"10.1145/75362.75425","DOIUrl":"https://doi.org/10.1145/75362.75425","url":null,"abstract":"ASIC microprocessors are becoming an important technology for the control of complex (“embedded”) systems. The advantage of such microprocessors is that they can be tailored to the application. This tailoring is quite non-intuitive and optimization is a complex process. Tools such as the Architect's Workbench (AWB) have been developed to assist in this optimization. An example study shows a more than two to one advantage of such assisted analysis.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132238192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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