MICRO 22Pub Date : 1989-08-01DOI: 10.1145/75362.75396
Kuarlall Lall, J. Atwood
{"title":"A microprogrammed interpreter for concurrent euclid","authors":"Kuarlall Lall, J. Atwood","doi":"10.1145/75362.75396","DOIUrl":"https://doi.org/10.1145/75362.75396","url":null,"abstract":"There are several methods of executing programs written in a high level language. The most widely used is to compile the programs into machine language. Another is to translate the programs into some intermediate form and then to execute that form interpretively. A third method is to directly execute either the HLL or the intermediate form.\u0000This study was aimed at investigating the feasibility of directly executing the intermediate representation of the sequential features of Concurrent Euclid (CE) on the SEL 32/75 computer. The CE intermediate code was translated into Ecode, and a microprogrammed interpreter for Ecode was designed and implemented on the SEL, and benchmarked against the compiler. For the CPU-bound prime number algorithm Sieve of Eratosthenes, the interpreter was measured to be about twice as slow as the compiler, due primarily to poor overlap within microinstructions. Ecode was then modified, and a new translator and interpreter designed and implemented. The same benchmark then yielded comparable results for both the interpreter and compiler. We project that further changes in Ecode design and hardware support would result in substantial Ecode efficiency gains.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121781482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 22Pub Date : 1989-08-01DOI: 10.1145/75362.75403
R. Parekhji, N. K. Nanda
{"title":"Design methodology and microdiagnostics development for a self-checking microprocessor","authors":"R. Parekhji, N. K. Nanda","doi":"10.1145/75362.75403","DOIUrl":"https://doi.org/10.1145/75362.75403","url":null,"abstract":"The conventional design of electronic circuits is intolerant to operational faults. Self-checking logic is aimed at online fault detection and can hence be incorporated to achieve reliable operation. In this paper, the design of a self-checking microprocessor is discussed. Self-checking strategies for different functional units are selectively and judiciously applied, and also modified wherever necessary, for the design of the register section, the arithmetic & logic unit and the control unit. A self-checking microprogrammed control unit, capable of supporting normal instruction execution concurrently with diagnostics, is developed. The design methodology has been applied to Intel's 8085A microprocessor as a case study to make it self-testing. Overheads involved have also been estimated.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115777179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 22Pub Date : 1989-08-01DOI: 10.1145/75362.75399
M. Brady
{"title":"A direct execution architecture for Prolog?","authors":"M. Brady","doi":"10.1145/75362.75399","DOIUrl":"https://doi.org/10.1145/75362.75399","url":null,"abstract":"This paper describes work in progress on the development of a direct execution Prolog processor.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123800015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 22Pub Date : 1989-08-01DOI: 10.1145/75362.75405
Y. Malaiya
{"title":"On inherent untestability of unaugmented microprogrammed control","authors":"Y. Malaiya","doi":"10.1145/75362.75405","DOIUrl":"https://doi.org/10.1145/75362.75405","url":null,"abstract":"Effective and efficient testing of the control part of a processor has remained a difficult problem. While several approaches have been proposed in the literature for handling unaugmented control parts, they involve questionable assumptions, and the results have not been encouraging. Here it is shown that unless some DFT (Design for Testability) approaches are taken, microprogrammed control is inherently a poorly testable structure. The considerations include lack of an elegant fault model, presence of components with low random testability, the length of a checking sequence and information-theoretic considerations. The design approaches must therefore include DFT augmentations and/or removal of sub-functional logic.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125473398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 22Pub Date : 1989-08-01DOI: 10.1145/75362.75404
Linda A. Kovacs, Steven F. Gilli
{"title":"Extended microcode error checking on a pipelined machine","authors":"Linda A. Kovacs, Steven F. Gilli","doi":"10.1145/75362.75404","DOIUrl":"https://doi.org/10.1145/75362.75404","url":null,"abstract":"In a pipelined computer, there is a possibility of interaction between microwords. These interactions may cause the operation of the computer to slow down, or they may cause errors. An extended error checking tool is used to detect these cases and help the microcode be more correct and more efficient.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117289646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 22Pub Date : 1989-08-01DOI: 10.1145/75362.75412
E. Sanchez
{"title":"A microprogramming teaching environment using the Macintosh computer","authors":"E. Sanchez","doi":"10.1145/75362.75412","DOIUrl":"https://doi.org/10.1145/75362.75412","url":null,"abstract":"A microprogramming teaching environment is presented. It is composed of a hardware part (a 16 bit microprogrammable processor) and a software part, running on a Macintosh II computer.\u0000The software includes 6 modules: two microassemblers - one uses a classical approach to generate microcode from a description in a register transfer language and the other one, which is more unusual, is menu-driven -; a disassembler; a monitor allowing one to display and modify the processor resources, as well as to control the execution; a memory loader and a simulator.\u0000The interactive and convivial nature of the Macintosh computer, and especially the HyperCard application, are used thoroughly in order to facilitate a utilization of the system.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"264 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121317540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 22Pub Date : 1989-08-01DOI: 10.1145/75362.75424
Edil S. T. Fernandes
{"title":"A model for microarchitecture structure evaluation","authors":"Edil S. T. Fernandes","doi":"10.1145/75362.75424","DOIUrl":"https://doi.org/10.1145/75362.75424","url":null,"abstract":"This paper presents the specification and implementation of a model oriented primarily to the evaluation of the structure of microarchitectures. According to the model, target architectures are described as an oriented graph which is examined by search algorithms in order to find the minimum cost path required in the execution of a set of machine primitives.\u0000The model is very useful to determine the role of each target machine component: through the model it is possible to assess the effect of both including and removing architecture components on the overall performance of a machine being conceived.\u0000The paper shows the main aspects of the project, discusses the research potential of the model, and describes the current stage of the work.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126273339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 22Pub Date : 1989-08-01DOI: 10.1145/75362.75408
R. Katti, L. Manwaring
{"title":"Information structures in language directed architectures","authors":"R. Katti, L. Manwaring","doi":"10.1145/75362.75408","DOIUrl":"https://doi.org/10.1145/75362.75408","url":null,"abstract":"Only recently has the design of computer architectures deviated from the Von Neumann style. Most architectures based on the Von Neumann architecture suffer from what is called 'the semantic gap'. This means that the objects and operations in a high level language (HLL) are not closely related to the objects and operations in the architectures that execute the HLL [1]. This paper addresses the issues involved in the semantic gap problem, by formulating a framework based on 'information structures' that would aid in the design of HLL architectures. First digital computers are defined based on 'information structures'. Execution of a program in an HLL is defined in terms of transformations on information structures. An architecture design methodology is proposed and some comments about performance are made. Finally different ways of implementing information structures are considered.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122268822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 22Pub Date : 1989-08-01DOI: 10.1145/75362.75406
G. Sechi
{"title":"Abstract computing machines","authors":"G. Sechi","doi":"10.1145/75362.75406","DOIUrl":"https://doi.org/10.1145/75362.75406","url":null,"abstract":"During last five years I have felt the need to possess powerful theoretical means of improving my designing capability by automating the production of operative implementations. This implies on one hand the identification and avoidance of the causes of errors, and on the other the rigorous definition of all the implementative phases in order to make unnecessary the use of ingenuity and creativity for the product implementation. Most computer-users consider the problems (i.e. errors, lack of documentation and a generallly low level of service ) in s/w and h/w as unavoidable, inherent “disasters”. Unlike them, I believe that these problems can be solved. In [I] we show that most designers and purchasers accept having to spend as much as 100% or 120% more than the time predicted and the cost of the definition, design and initial manifacturing, stages, merely in order to achieve an acceptable product. Delays, efforts, and energy spent on meeting the requirements and the product during the test and the error-avoidance stage, yield a new product. This product conforms to specifications, requirements and financial evaluations that are completely different from the original and, in general, expensive compared to the environment from which the design originated. The errors due to indeterminate specifications, to the imprecisions inherent in working practice, and in basic tools such as programming language, operating systems, or electronic components, al,d the impossibility of exhaustive testing for purposes of experimental validation and fault avoidance are the cause of growing costs. Indeed, there is an unpredictable interval between identification of the needs of a computing system and its actually becoming available.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124170570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 22Pub Date : 1989-08-01DOI: 10.1145/75362.75416
J. Linn, C. Ardoin
{"title":"All example of using pseudofields to eliminate version shuffling in horizontal code compaction","authors":"J. Linn, C. Ardoin","doi":"10.1145/75362.75416","DOIUrl":"https://doi.org/10.1145/75362.75416","url":null,"abstract":"This paper first reviews the version shuffling problem for microcode compaction. Next, a somewhat representative compaction problem involving asymmetric ALUs and a port-limited register file is presented. Finally, the paper shows how to model the architecture in a microcode compiler using the concept of pseudofields. While the modeling process is nontrivial, it is seen that this approach solves the version shuffling problem without introducing early-binding inefficiencies in the compiled code.","PeriodicalId":365456,"journal":{"name":"MICRO 22","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130593372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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