2018 International Integrated Reliability Workshop (IIRW)最新文献_第3页

Fast Power-Temperature Cycling of BEOL Test Structures for Power Devices 功率器件BEOL测试结构的快速功率-温度循环

2018 International Integrated Reliability Workshop (IIRW) Pub Date : 2018-10-01 DOI: 10.1109/IIRW.2018.8727079

M. Ring, B. Cowell, D. Moore, J. Gambino

引用次数: 1

Investigation of the effects of Pulsed Direct Current at low frequencies on the Electromigration Lifetime : Student Paper 低频脉冲直流电对电迁移寿命影响的研究:学生论文

2018 International Integrated Reliability Workshop (IIRW) Pub Date : 2018-10-01 DOI: 10.1109/IIRW.2018.8727088

J. M. Passage, S. Rogalskyj, N. Azhari, E. Wilcox, J. Lloyd

{"title":"Investigation of the effects of Pulsed Direct Current at low frequencies on the Electromigration Lifetime : Student Paper","authors":"J. M. Passage, S. Rogalskyj, N. Azhari, E. Wilcox, J. Lloyd","doi":"10.1109/IIRW.2018.8727088","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727088","url":null,"abstract":"Accelerated electromigration (EM) testing generally utilizes a constant direct current (DC). However, in operation or “real life” the metal interconnect is commonly exposed to an alternating current (AC) or pulsed direct current (PDC). If at all, compensation for the use of PDC failure is measured by the ‘time-on’ current stress and then modeled as a linear multiple of the duty cycle (percentage of time-on current) [1], [2]. EM life-time is determined by an electromigration driving force as well as a current-induced mechanical stress gradient driving force. In the event current was interrupted or turned off for a period, the stress gradient driving force would continue to act. In the event a void is nucleated, the stress gradient that once opposed EM, would work in the same direction.We studied the failure of copper interconnects using a low frequency pulsed direct current, 10 Hz. We investigated the effects of the duty cycle, and current on the EM failure behavior using PDC and compared the results to accelerated testing preformed with constant direct current. From the comparison of PDC and DC accelerated testing, it is shown that at low current densities, PDC stressed devices show extended lifetime of interconnects and at high current densities (above 8 MA/cm2), they showed a reduced lifetime of the interconnects.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126063405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Aging control of power amplifier using power detector 基于功率检测器的功放老化控制

2018 International Integrated Reliability Workshop (IIRW) Pub Date : 2018-10-01 DOI: 10.1109/IIRW.2018.8727098

R. Lajmi, F. Cacho, V. Knopik, P. Cathelin, J. Lugo, P. Benech, E. L. Larroze, S. Bourdel, X. Federspiel

引用次数: 0

Synaptic Behavior of Nanoscale ReRAM Devices for the Implementation in a Dynamic Neural Network Array 动态神经网络阵列中实现的纳米级ReRAM器件的突触行为

2018 International Integrated Reliability Workshop (IIRW) Pub Date : 2018-10-01 DOI: 10.1109/IIRW.2018.8727104

K. Beckmann, W. Olin-Ammentorp, Sierra Russell, Nadia Suguitan, C. Hobbs, M. Rodgers, N. Cady, G. Rose, J. V. Van Nostrand

{"title":"Synaptic Behavior of Nanoscale ReRAM Devices for the Implementation in a Dynamic Neural Network Array","authors":"K. Beckmann, W. Olin-Ammentorp, Sierra Russell, Nadia Suguitan, C. Hobbs, M. Rodgers, N. Cady, G. Rose, J. V. Van Nostrand","doi":"10.1109/IIRW.2018.8727104","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727104","url":null,"abstract":"Resistive random access memory (ReRAM) is a new form of non-volatile memory that has the potential to replace Flash memory or augment the current memory hierarchy. In addition, novel circuit architectures have been proposed that rely on newly discovered or predicted behavior of ReRAM devices. One such architecture is the memristive Dynamic Adaptive Neural Network Array (mrDANNA), developed to emulate the functionality of a biological neural network. This architecture relies on synapses which are capable of changing their resistance in an analog fashion by applying ultra-short pulses. We demonstrate ReRAM devices that show this tendency. The ReRAM devices shown here are based on an HfO2 switching layer that sits on a tungsten bottom electrode, is covered by a titanium oxygen scavenger layer, a titanium nitride top electrode, and are structured to a size of 100×100 nm2. In this work, we show devices that exhibit incremental resistance changes in a synaptic fashion and can switch using pulses as short as 5 ns. A major hurdle is the variability observed with these devices and its effect on the designed mrDANNA architecture. One focus of the ongoing work is a simulation on the effect of the observed variability. For this purpose, a Monte Carlo simulation with extracted variability data are being performed to demonstrate the impact on this neuromorphic architecture.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115378115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

IIRW 2018 Summaries of Invited Papers iirw2018特邀论文摘要

2018 International Integrated Reliability Workshop (IIRW) Pub Date : 2018-10-01 DOI: 10.1109/iirw.2018.8727090

引用次数: 0

On the Impact of the Gate Metal Work-Function on the Charge Trapping Component of BTI 栅极金属工作功能对BTI电荷俘获元件的影响

2018 International Integrated Reliability Workshop (IIRW) Pub Date : 2018-10-01 DOI: 10.1109/IIRW.2018.8727089

J. Franco, Z. Wu, G. Rzepa, L. Ragnarsson, H. Dekkers, A. Vandooren, G. Groeseneken, N. Horiguchi, N. Collaert, D. Linten, T. Grasser, B. Kaczer

引用次数: 0

Border Trap Based Modeling of SiC Transistor Transfer Characteristics 基于边界陷阱的SiC晶体管转移特性建模

2018 International Integrated Reliability Workshop (IIRW) Pub Date : 2018-10-01 DOI: 10.1109/IIRW.2018.8727083

S. Tyaginov, M. Jech, G. Rzepa, A. Grill, A. El-Sayed, G. Pobegen, A. Makarov, T. Grasser

{"title":"Border Trap Based Modeling of SiC Transistor Transfer Characteristics","authors":"S. Tyaginov, M. Jech, G. Rzepa, A. Grill, A. El-Sayed, G. Pobegen, A. Makarov, T. Grasser","doi":"10.1109/IIRW.2018.8727083","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727083","url":null,"abstract":"We experimentally and theoretically study the impact of interface and border traps on the transfer characteristics of 4H-SiC transistors measured over a wide temperature range of 200-350 K. Quite apparently, the experimental current-voltage characteristics have drain currents which are much lower than those obtained from simulations performed without traps. Moreover, currents increase with temperature over the entire gate voltage range, while the threshold voltage shifts towards lower values as temperature increases. We show that although interface traps can explain ${I}_{{mathrm {d}}}-{V}_{{mathrm {gs}}}$ curves measured at room temperature with good accuracy it fails for lower temperatures. Inclusion of border traps, on the other hand, results in good agreement between experimental and simulated current-voltage characteristics over the entire temperature range. For the first time we were able to successfully represent transfer characteristics of a 4H-SiC transistor at temperatures substantially below 300 K. Therefore, we conclude that border traps are responsible for the complicated behavior of $mathrm{I}_{{mathrm {d}}}-mathrm{V}_{{mathrm {gs}}}$ characteristics.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114316723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Reliability of High Speed Photodetector for Silicon Photonic Applications 用于硅光子应用的高速光电探测器的可靠性

2018 International Integrated Reliability Workshop (IIRW) Pub Date : 2018-10-01 DOI: 10.1109/IIRW.2018.8727087

F. Sy, Q. Rafhay, C. Besset, G. Beylier, P. Grosse, D. Roy, J. Broquin

引用次数: 1

Multiple Modes of Electromigration Failure in SAC Solder Alloys SAC钎料合金的多模式电迁移失效

2018 International Integrated Reliability Workshop (IIRW) Pub Date : 2018-10-01 DOI: 10.1109/IIRW.2018.8727066

Deborah Noble, M. Ring, J. Lloyd

引用次数: 0

IIRW 2018 Discussion Group: Product reliability for Low-Volume, High-Consequence Integrated-Circuits Fabrication IIRW 2018讨论小组:小批量，高结果集成电路制造的产品可靠性

2018 International Integrated Reliability Workshop (IIRW) Pub Date : 2018-10-01 DOI: 10.1109/iirw.2018.8727068

引用次数: 0