2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第9页

Clock Gating Synthesis of Netlist with Cyclic Logic Paths 循环逻辑路径网表的时钟门控综合

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2019-11-01 DOI: 10.1109/iccad45719.2019.8942042

Yonghwi Kwon, Inhak Han, Youngsoo Shin

引用次数: 0

SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks 软处理器系统上的安全随机时钟执行以减轻基于功率的侧信道攻击

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2019-11-01 DOI: 10.1109/iccad45719.2019.8942112

Darshana Jayasinghe, A. Ignjatović, S. Parameswaran

{"title":"SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks","authors":"Darshana Jayasinghe, A. Ignjatović, S. Parameswaran","doi":"10.1109/iccad45719.2019.8942112","DOIUrl":"https://doi.org/10.1109/iccad45719.2019.8942112","url":null,"abstract":"Power-based side channel attacks are effective in revealing the secret keys of cryptographic algorithm implementations running on soft processor systems. This paper, for the first time, proposes a clock random execution methodology (referred to as SCRIP) to execute a soft processor core and most of the components (some components cannot be executed with a random clock frequency). An open source soft processor system (LowRISC which is based on the RISC-V Instruction Set Architecture) has been executed with the proposed SCRIP clock random execution methodology. Power analysis attacks (including preprocessing techniques to remove the effects of random execution) were carried out against the SCRIP LowRISC soft processor implementation to test the effects of random clock execution. SCRIP LowRISC implementation is shown to be secure for up to 300,000 encryptions, while the LowRISC implementation without SCRIP revealed the secret key within 1,000 encryptions. The result of information leakage test shows that the secret key cannot be recovered with 99.999% confidence level. Compared to other soft core processor countermeasures, SCRIP LowRISC implementation has the smallest complete soft processor system with 1.04× resource overhead (the smallest hardware masking countermeasure, which is applied to only the ALU of a RISC-V processor has 1.59× resource overhead, and the smallest balancing countermeasure soft processor, with the countermeasure applied only to the ALU and the memory, required 1.15× area overhead) where the security against power analysis attacks is applied to most components of the processor (including ALU, caches, Block RAM, Block RAM controller, bus interconnect and SD card interface). SCRIP LowRISC implementation is the first soft processor with a random execution-based countermeasure to withstand preprocessing methods (such as power trace alignment and noise filtering) which remove the effects of random execution.","PeriodicalId":363364,"journal":{"name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1078 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126894813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Exploiting Randomness in Stochastic Computing 利用随机计算中的随机性

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2019-11-01 DOI: 10.1109/iccad45719.2019.8942138

Pai-Shun Ting, J. Hayes

{"title":"Exploiting Randomness in Stochastic Computing","authors":"Pai-Shun Ting, J. Hayes","doi":"10.1109/iccad45719.2019.8942138","DOIUrl":"https://doi.org/10.1109/iccad45719.2019.8942138","url":null,"abstract":"Stochastic computing (SC) computes with randomized bit-streams using standard logic circuits. Its defining features are low power, small area, and high fault tolerance; its drawbacks are long run times and inaccuracies due to its inherently random behavior. Consequently, much previous work has focused on improving SC performance by introducing non-random or deterministic data formats and components, often at considerable cost. However, as this paper shows, taking advantage of, or even adding to, a stochastic circuit's randomness can play a major positive role in applications like neural networks (NNs). The amount of such randomness, must however, be carefully controlled to achieve a beneficial effect without corrupting an application's functionality. The paper first discusses the use of mean square deviation (MSD) as a metric for randomness in SC. It then describes a low-cost element to control the MSD levels of stochastic signals. Finally, it examines two applications where SC can provide performance-enhancing randomness at very low cost, while retaining all the other benefits of SC. Specifically, it is shown how to improve the visual quality of black-and-white images via stochastic dithering, a technique that leverages randomness to enhance image details. Further, the paper demonstrates how the randomness of an SC-based layer makes an NN more resilient against adversarial attacks than an NN realized entirely by conventional, non-stochastic designs.","PeriodicalId":363364,"journal":{"name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128057337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction Dr. CU 2.0:一个可扩展的详细路由框架，符合正确的结构设计规则

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2019-11-01 DOI: 10.1109/iccad45719.2019.8942074

Haocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen, Evangeline F. Y. Young

引用次数: 35

Adar: Adversarial Activity Recognition in Wearables Adar:可穿戴设备中的对抗活动识别

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2019-11-01 DOI: 10.1109/iccad45719.2019.8942124

Ramesh Kumar Sah, Hassan Ghasemzadeh

{"title":"Adar: Adversarial Activity Recognition in Wearables","authors":"Ramesh Kumar Sah, Hassan Ghasemzadeh","doi":"10.1109/iccad45719.2019.8942124","DOIUrl":"https://doi.org/10.1109/iccad45719.2019.8942124","url":null,"abstract":"Recent advances in machine learning and deep neural networks have led to the realization of many important applications in the area of personalized medicine. Whether it is detecting activities of daily living or analyzing images for cancerous cells, machine learning algorithms have become the dominant choice for such emerging applications. In particular, the state-of-the-art algorithms used for human activity recognition (HAR) using wearable inertial sensors utilize machine learning algorithms to detect health events and to make predictions from sensor data. Currently, however, there remains a gap in research on whether or not and how activity recognition algorithms may become the subject of adversarial attacks. In this paper, we take the first strides on (1) investigating methods of generating adversarial example in the context of HAR systems; (2) studying the vulnerability of activity recognition models to adversarial examples in feature and signal domain; and (3) investigating the effects of adversarial training on HAR systems. We introduce Adar11Software code and experimental data for Adar are available online at https://github.com/rameshKrSah/Adar., a novel computational framework for optimization-driven creation of adversarial examples in sensor-based activity recognition systems. Through extensive analysis based on real sensor data collected with human subjects, we found that simple evasion attacks are able to decrease the accuracy of a deep neural network from 95.1% to 3.4% and from 93.1% to 16.8% in the case of a convolutional neural network. With adversarial training, the robustness of the deep neural network increased on the adversarial examples by 49.1% in the worst case while the accuracy on clean samples decreased by 13.2%.","PeriodicalId":363364,"journal":{"name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121888361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper 利用CoSA和符号QED解锁正式硬件验证的力量:特邀论文

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2019-11-01 DOI: 10.1109/iccad45719.2019.8942096

Florian Lonsing, K. Ganesan, Makai Mann, Srinivasa Shashank Nuthakki, Eshan Singh, Mario Srouji, Yahan Yang, S. Mitra, Clark W. Barrett

{"title":"Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper","authors":"Florian Lonsing, K. Ganesan, Makai Mann, Srinivasa Shashank Nuthakki, Eshan Singh, Mario Srouji, Yahan Yang, S. Mitra, Clark W. Barrett","doi":"10.1109/iccad45719.2019.8942096","DOIUrl":"https://doi.org/10.1109/iccad45719.2019.8942096","url":null,"abstract":"As designs grow in size and complexity, design verification becomes one of the most difficult and costly tasks facing design teams. Formal verification techniques offer great promise because of their ability to exhaustively explore design behaviors. However, formal techniques also have a reputation for being labor-intensive and limited to small blocks. Is there any hope for successful application of formal techniques at design scale? We answer this question affirmatively by digging deeper to understand what the real technological issues and opportunities are. First, we look at satisfiability solvers, the engines underlying formal techniques such as model checking. Given the recent innovations in satisfiability solving, we argue that there are many reasons to be optimistic that formal techniques will scale to designs of practical interest. We use our CoSA model checker as a demonstration platform to illustrate how advances in solvers can improve scalability. However, even if solvers become blazingly fast, applying them well is still labor-intensive. This is because formal tools are only as useful as the properties they are given to prove, which traditionally have required great effort to develop. Symbolic quick error detection (SQED) addresses this issue by using a single, universal property that checks designs automatically. We demonstrate how SQED can automatically find logic and security bugs in a variety of designs and report on bugs found and efficiency gains realized in academic and industry designs. We also present a generator for an improved SQED module that further reduces the amount of manual effort that has to be spent by the designer.","PeriodicalId":363364,"journal":{"name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127976567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper 新兴技术对架构和系统级管理的影响:特邀论文

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2019-11-01 DOI: 10.1109/iccad45719.2019.8942102

J. Henkel, H. Amrouch, Martin Rapp, Sami Salamin, D. Reis, Di Gao, Xunzhao Yin, M. Niemier, Cheng Zhuo, X. Hu, Hsiang-Yun Cheng, Chia-Lin Yang

{"title":"The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper","authors":"J. Henkel, H. Amrouch, Martin Rapp, Sami Salamin, D. Reis, Di Gao, Xunzhao Yin, M. Niemier, Cheng Zhuo, X. Hu, Hsiang-Yun Cheng, Chia-Lin Yang","doi":"10.1109/iccad45719.2019.8942102","DOIUrl":"https://doi.org/10.1109/iccad45719.2019.8942102","url":null,"abstract":"The goal of this work is to introduce and discuss different kinds of emerging technologies for logic circuitry and memory with respect to the key question of how they will impact future system-on-chip architectures and system-level management techniques. It is obvious that emerging technologies should have an impact there in order to fully exploit their technological advantages but also in order to deal with any disadvantages they might come with. In this special session paper, three promising emerging technologies are presented: (i) Negative Capacitance Field-Effect Transistor (NCFET) as a new CMOS technology with advantages primarily for low-power design, (ii) Ferroelectric FET (FeFET) as a non-volatile, area-efficient and low-power combined logic and memory as well as (iii) a Phase-Change Memory (PCM) and Resistive RAM (ReRAM) offering a large potential for tackling the memory wall problem in the von Neumann architecture. Our analysis demonstrates that not only new computing paradigms are promoted by these new technologies, it will also be seen that the trade-offs between the classical design parameters of low power, performance etc. will shift and hence emerging technologies will offer new Pareto points in the design space of future on-chip architectures. In that context, this work is unique as it bridges the gap between the technology side and system/architecture-level side to draw a vision of new technologies and their impact on architectures and system-level management.","PeriodicalId":363364,"journal":{"name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121029133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Towards In-Circuit Tuning of Deep Learning Designs 面向深度学习设计的在线调谐

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2019-11-01 DOI: 10.1109/iccad45719.2019.8942117

Zhiqiang Que, D. H. Noronha, Ruizhe Zhao, S. Wilton, W. Luk

引用次数: 2

Towards Verification-Aware Knowledge Distillation for Neural-Network Controlled Systems: Invited Paper 面向神经网络控制系统的验证感知知识蒸馏:特邀论文

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2019-11-01 DOI: 10.1109/iccad45719.2019.8942059

Jiameng Fan, Chao Huang, Wenchao Li, Xin Chen, Qi Zhu

引用次数: 12

Specification, Integration, and Benchmarking of Continuous Flow Microfluidic Devices: Invited Paper 连续流微流体装置的规范、集成和基准测试:特邀论文

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2019-11-01 DOI: 10.1109/iccad45719.2019.8942171

R. Sanka, Brian Crites, Jeffrey McDaniel, P. Brisk, D. Densmore

{"title":"Specification, Integration, and Benchmarking of Continuous Flow Microfluidic Devices: Invited Paper","authors":"R. Sanka, Brian Crites, Jeffrey McDaniel, P. Brisk, D. Densmore","doi":"10.1109/iccad45719.2019.8942171","DOIUrl":"https://doi.org/10.1109/iccad45719.2019.8942171","url":null,"abstract":"The lack of standardization in the specification and representation of microfluidic designs and their corresponding architectures is one of the largest hurdles faced by the developers of Microfluidic Design Automation (MDA) tools. In this paper, we introduce MINT, a Microfluidic Hardware Description Language (MHDL) for defining components and devices in a human readable manner, and ParchMint, an MDA interchange format and associated benchmark suite that can be used to compare the performance of different physical design algorithms. We further demonstrate how the introduction of MINT and ParchMint into the engineering workflow can bridge the gaps from the specification to the fabrication of microfluidic devices. While recent efforts to democratize microfluidics have been recognized by the community, there is an unfortunate lack of open source tools, design languages, and standards. Consequently, microfluidic designs shared on open platforms such as Metafluidics[15] leave conceptual gaps in terms of missing design information that are necessary to realize the “creative process flows” (Reproduce, Remix, and Test multiple systems). MINT and ParchMint are open source projects, which allows the community to contribute and extend their functionality to enable advanced algorithmic methodologies and new commercialization possibilities that differ from the vertically integrated industries we see today.","PeriodicalId":363364,"journal":{"name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130216250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5