2007 Asia and South Pacific Design Automation Conference最新文献_第4页

Bisection Based Placement for the X Architecture X架构的基于平分的布局

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357978

S. Ono, S. Tilak, P. Madden

引用次数: 3

Recognition of Fanout-free Functions 无风扇输出功能的识别

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358023

Tsung-Lin Lee, Chun-Yao Wang

引用次数: 8

Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic 基于互补铁电-电容逻辑的备用无电凸轮的实现

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357968

S. Matsunaga, T. Hanyu, H. Kimura, Takashi Nakamura, H. Takasu

引用次数: 3

A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications 面向图像处理应用的高级综合参数化体系结构模型

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358039

Yazhuo Dong, Y. Dou

引用次数: 8

Systematic Scan Reconfiguration 系统扫描

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358075

Ahmad A. Al-Yamani, Narendra Devta-Prasanna, A. Gunda

引用次数: 2

A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms 噪声输入波形下基于电流的短路功率计算方法

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358083

H. Fatemi, Shahin Nazarian, Massoud Pedram

{"title":"A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms","authors":"H. Fatemi, Shahin Nazarian, Massoud Pedram","doi":"10.1109/ASPDAC.2007.358083","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358083","url":null,"abstract":"An accurate model is presented to calculate the short circuit energy dissipation of logic cells. The short circuit current is highly dependent on the input and output voltage values. Therefore the actual shape of the voltage signal waveforms at the input and output of the cell should be considered in order to precisely calculate the short circuit energy dissipation. Previous approaches such as the approximation of the crosstalk induced noisy waveforms with saturated ramps can lead to short circuit energy estimation errors as high as an order of magnitude for a minimum sized inverter. To resolve this shortcoming, a current-based logic cell model is utilized, which constructs the output voltage waveform for a given noisy input waveform. The input and output voltage waveforms are then used to calculate the short circuit current, and hence, short circuit energy dissipation. A characterization process is executed for each logic cell in the standard cell library to model the relevant electrical parameters e.g., the parasitic capacitances and nonlinear current sources. Additionally, our model is capable of calculating the short circuit energy dissipation caused by glitches in VLSI circuits, which in some cases can be a key contributor to the total circuit energy dissipation. Experimental results show an average error of about 1% and a maximum error of 3% compared to SPICE for different types of logic cells under noisy input waveforms including glitches while the runtime speedup is up to a factor of 16,000.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125422177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond 3G及以上多标准Turbo解码器的VLSI设计

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358050

Imran Ahmed, T. Arslan

引用次数: 12

Psuedo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems 车载雷达系统带片上Balun的伪毫米波上转换混频器

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357963

I. Lai, M. Fujishima

引用次数: 1

System Architecture for Software Peripherals 软件外设的系统架构

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357792

S. Choudhuri, T. Givargis

引用次数: 1

Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier" 基于UniPhier集成平台的移动应用soc低功耗技术

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358060

M. Nakajima, Takao Yamamoto, M. Yamasaki, T. Hosoki, M. Sumita

{"title":"Low Power Techniques for Mobile Application SoCs Based on Integrated Platform \"UniPhier\"","authors":"M. Nakajima, Takao Yamamoto, M. Yamasaki, T. Hosoki, M. Sumita","doi":"10.1109/ASPDAC.2007.358060","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358060","url":null,"abstract":"In this paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform \"UniPhier\". To minimize SoC power dissipation, hierarchical approaches from UniPhier Soc level, UniPhier processor level, IPP (instruction parallel processor) level, and circuit level are adopted. As SoC level, 1) well functionally isolated 5 major units of UniPhier SoC architecture, 2) dedicated stream DMA controller which can minimize CPU load and memory access. As UniPhier processor level, 1) UniPhier processor consists of IPP with dedicated low power hardware engine, 2) VMP (virtual multi-processor) mechanism with micro sleep which can reduce average power consumption in case of multiple tasks concurrent operation, 3) intermittent operation with the combination of micro-sleep and clock/power down scheme in case of very light load operation. As IPP level, 1) sophisticated instruction fetch buffer mechanism which can reduce more than 50% memory access for instruction fetch. 2) Hierarchical and selective clock gating scheme by detailed clock power analysis and clock activity rate analysis on real application.) Optimized physical implementation with low-power library and selective use of custom macros. As circuit level, mixed body bias technique with fixed Id and fixed Vt control which can realize 85 % delay variation suppressed and 25% ED product improvement compared with the no body bias.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130604187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12