The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory最新文献
{"title":"ATM Adaptation Layer Issues","authors":"A. Nilsson, Zhi Cui","doi":"10.1109/SSST.1992.712329","DOIUrl":"https://doi.org/10.1109/SSST.1992.712329","url":null,"abstract":"The impact of the Convergence Suldayer Protocol Data Unit (CS-PDU) size on the end-to-end network delay in a B-ISDN environment is investigated in this paper. Cell loss probabilities are assumed to be bursty and when a cell loss occurs a retransmission on the CS-PDU level will be done. The network has been simulated and the simulation results indicate that it is possible to select a CS-PDU size that will minimize the end-to-end delay. A typical ATM network has also been analyzed by using mathematical modeling technique. Assuming Poisson arrival process, it is possible to compute approximately the end-to-end delay as a function of the CS-PDU size. It can then be shown that the delay is optimized for a particular CS-PDU size.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132902344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Matched Field Processing: An Overview","authors":"H. B. Riley, J. Tague","doi":"10.1109/SSST.1992.712256","DOIUrl":"https://doi.org/10.1109/SSST.1992.712256","url":null,"abstract":"Matched-field processing has produced promising results in seismic, radar, and underwater acoustics applications. This paper reviews the localization of acoustic sources via matched-field processing. A new method for source localization in a stochastic medium is presented. This method has an \"estimator-correlator\" structure and is based upon rudimental detection and estimation theory.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133125361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Robust Control of a Vibrating Link Robot Manipulator","authors":"D. Shukla, D. Dawson, F. Paul","doi":"10.1109/SSST.1992.712376","DOIUrl":"https://doi.org/10.1109/SSST.1992.712376","url":null,"abstract":"This paper presents an approach for designing robust tracking controller for lumped mass model of a vibrating link (VL) robot manipulator. The control methodology is intuitively simple since it is based on concepts which are familiar to most control engineers. The approach is illustrated by developing a robust tracking controller that achieves global uniform ultimate boundedness (GUUB) stability of the link tracking error in spite of model uncertainty and the additional link dynamics.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121522267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Compact Finite Volume Scheme for 2-D Stefan Problems and Vector/Multiprocessor Computers","authors":"R. White, B. N. Borah, A. Kyrillidis","doi":"10.1109/SSST.1992.712259","DOIUrl":"https://doi.org/10.1109/SSST.1992.712259","url":null,"abstract":"We consider both the compact finite volume and finite difference space discretizations of the Stefan problem. The resulting algebraic systems are solved by nonlinear versions of ADI and SOR. Both algorithms contain significant parallelism which is demonstrated on two vector/multiprocessing computers, the Alliant FX/40 and the Cray Y-MP. Numerical experiments indicate that the compact discretization and ADI give the best accuracy with the minimum computational cost.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121865956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Bridging Behavioral and Register-Transfer Synthesis","authors":"S. Bhattacharya, F. Brglez","doi":"10.1109/SSST.1992.712208","DOIUrl":"https://doi.org/10.1109/SSST.1992.712208","url":null,"abstract":"This paper considers register-transfer synthesis and optimization from a control-data flowgraph specification. In contrast to scheduling under resource constraints, we derive a register-transfer (RT) description without imposing constraints on resources. The initial RT-level description may seem to have an excessive number of functional units and multiplexors, however it will typically exhibit also high signal reconvergence. We demonstrate with non-trivial benchmark examples that regions of high signal reconvergence offer high resynthesis and optimization potential also at RT-level, producing standard cell realizations that are comparable and competitive with alternate approaches in all aspects: layout area, path delay and gate-level testability. Tradeoffs in resource allocation are examined at RT-level only after optimizing the initial description. The RT-level description we generate serves as a top-level input to OASIS, which expands it to the required data-path components, synthesizes all control specifications, performs test generation and global optimization by redundancy removal and submits the final standard cell netlist for automatic placement and routing.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129621790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Computer Communications: Ideas and Trends","authors":"D. Winkelstein","doi":"10.1109/SSST.1992.712177","DOIUrl":"https://doi.org/10.1109/SSST.1992.712177","url":null,"abstract":"Broadband Integrated Service Digital Network (BISDN) is an emerging high speed telecommunication standard for the next generation of high-sped wide- and local-area networks. This method of information transfer will not only change the way computers communicate but also will change the way we solve problems. Within this paper we detail our vision the way high-speed communication networks will be organized and will operate. We will then outline some of the effect these high speed networks will have on the communications protocol stack.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132768085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CAzM 5.0- A Robust, Table-Based Analog Circuit Simulator","authors":"W. Richards","doi":"10.1109/SSST.1992.712334","DOIUrl":"https://doi.org/10.1109/SSST.1992.712334","url":null,"abstract":"CAzM (Circuit Analyzer with Macro-modeling) is a robust, table-based analog circuit simulator employing modern numerical techniques to improve convergence and operating efficiency. It allows devices to be modeled via current and charge vs. voltage tables for minimal CPU usage, or analytic function calls may be used directly for maximum accuracy. CAzM 5.0 will be discussed here, outlining new features as well as performance data compared to HSPICE.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130432429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CALLAS/OASIS: Combining Behavioral and Register-Transfer Synthesis Systems","authors":"M. Pilsl, F. Brglez","doi":"10.1109/SSST.1992.712211","DOIUrl":"https://doi.org/10.1109/SSST.1992.712211","url":null,"abstract":"While behavioral synthesis has still to prove its feasibility in an industrial environment, register-transfer level synthesis is already accepted. Especially, behavioral synthesis has to compete with state of the art register-transfer synthesis in terms of area and timing of the synthesized chips. We have performed several controlled benchmark experiments, using test examples and chip designs that range from 300 to 50,000 transistors. Our results demonstrate that behavioral synthesis can generate logic and layout with performance which is comparable to those produced from register-transfer descriptions provided by a designer.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127508271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multilevel Metal Using Submicron Copper Interconnects","authors":"B. Rogers, S. Bothra, S. Bobbio, M. Kellam","doi":"10.1109/SSST.1992.712179","DOIUrl":"https://doi.org/10.1109/SSST.1992.712179","url":null,"abstract":"A copper-based multilevel metallurgy potentially offers very significant benefits compared to the aluminum alloys and barrier layers that currently are being used in ultralarge-scale integrated (ULSI) technology. However, before copper can be successfully integrated into ULSI systems, a number of important reliability and processing issues must be addressed. At MCNC, a comprehensive program is underway to develop an integrated copper metallurgy process. In this paper, an analysis of the effects of scaling on interconnect delay is given, demonstrating the potential benefits of a copper metallurgy for ULSI circuits. Then, work toward the development of an integrated copper metallurgy process is presented, including copper etching results, a copper cladding methodology to alleviate reliability problems, and a novel via chain structure.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126694608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enhancing Computer Engineering Education with Verilog/suo R/ HDL","authors":"D. Jackson, S.J. Hannah","doi":"10.1109/SSST.1992.712207","DOIUrl":"https://doi.org/10.1109/SSST.1992.712207","url":null,"abstract":"A hardware description language (HDL) has been introduced in a senior-level computer engineering course to promote the understanding of computer organization and design at the register-transfer and the gate level. This paper describes various components of the HDL and the pedagogical aspects of its incorporation into an existing course. Additionally, completed student projects and comments from a student questionnaire are analyzed to access the students' knowledge of computer engineering fundamentals and to determine if this knowledge is enhanced or diminished by the incorporation of a HDL into the design component of the course. These analyses subsequently justify the study of, and inclusion of a HDL as a part of the design component for courses spanning an undergraduate computer engineering sequence.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126750882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}