{"title":"架起行为与语域迁移综合的桥梁","authors":"S. Bhattacharya, F. Brglez","doi":"10.1109/SSST.1992.712208","DOIUrl":null,"url":null,"abstract":"This paper considers register-transfer synthesis and optimization from a control-data flowgraph specification. In contrast to scheduling under resource constraints, we derive a register-transfer (RT) description without imposing constraints on resources. The initial RT-level description may seem to have an excessive number of functional units and multiplexors, however it will typically exhibit also high signal reconvergence. We demonstrate with non-trivial benchmark examples that regions of high signal reconvergence offer high resynthesis and optimization potential also at RT-level, producing standard cell realizations that are comparable and competitive with alternate approaches in all aspects: layout area, path delay and gate-level testability. Tradeoffs in resource allocation are examined at RT-level only after optimizing the initial description. The RT-level description we generate serves as a top-level input to OASIS, which expands it to the required data-path components, synthesizes all control specifications, performs test generation and global optimization by redundancy removal and submits the final standard cell netlist for automatic placement and routing.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Bridging Behavioral and Register-Transfer Synthesis\",\"authors\":\"S. Bhattacharya, F. Brglez\",\"doi\":\"10.1109/SSST.1992.712208\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper considers register-transfer synthesis and optimization from a control-data flowgraph specification. In contrast to scheduling under resource constraints, we derive a register-transfer (RT) description without imposing constraints on resources. The initial RT-level description may seem to have an excessive number of functional units and multiplexors, however it will typically exhibit also high signal reconvergence. We demonstrate with non-trivial benchmark examples that regions of high signal reconvergence offer high resynthesis and optimization potential also at RT-level, producing standard cell realizations that are comparable and competitive with alternate approaches in all aspects: layout area, path delay and gate-level testability. Tradeoffs in resource allocation are examined at RT-level only after optimizing the initial description. The RT-level description we generate serves as a top-level input to OASIS, which expands it to the required data-path components, synthesizes all control specifications, performs test generation and global optimization by redundancy removal and submits the final standard cell netlist for automatic placement and routing.\",\"PeriodicalId\":359363,\"journal\":{\"name\":\"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SSST.1992.712208\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SSST.1992.712208","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Bridging Behavioral and Register-Transfer Synthesis
This paper considers register-transfer synthesis and optimization from a control-data flowgraph specification. In contrast to scheduling under resource constraints, we derive a register-transfer (RT) description without imposing constraints on resources. The initial RT-level description may seem to have an excessive number of functional units and multiplexors, however it will typically exhibit also high signal reconvergence. We demonstrate with non-trivial benchmark examples that regions of high signal reconvergence offer high resynthesis and optimization potential also at RT-level, producing standard cell realizations that are comparable and competitive with alternate approaches in all aspects: layout area, path delay and gate-level testability. Tradeoffs in resource allocation are examined at RT-level only after optimizing the initial description. The RT-level description we generate serves as a top-level input to OASIS, which expands it to the required data-path components, synthesizes all control specifications, performs test generation and global optimization by redundancy removal and submits the final standard cell netlist for automatic placement and routing.