Enhancing Computer Engineering Education with Verilog/suo R/ HDL

Abstract

A hardware description language (HDL) has been introduced in a senior-level computer engineering course to promote the understanding of computer organization and design at the register-transfer and the gate level. This paper describes various components of the HDL and the pedagogical aspects of its incorporation into an existing course. Additionally, completed student projects and comments from a student questionnaire are analyzed to access the students' knowledge of computer engineering fundamentals and to determine if this knowledge is enhanced or diminished by the incorporation of a HDL into the design component of the course. These analyses subsequently justify the study of, and inclusion of a HDL as a part of the design component for courses spanning an undergraduate computer engineering sequence.