International Journal of High Speed Electronics and Systems最新文献_第7页

Image Super-Resolution Reconstruction Model Based on Multi-Feature Fusion 基于多特征融合的图像超级分辨率重建模型

International Journal of High Speed Electronics and Systems Pub Date : 2024-01-23 DOI: 10.1142/s0129156424400032

Zemiao Dai

{"title":"Image Super-Resolution Reconstruction Model Based on Multi-Feature Fusion","authors":"Zemiao Dai","doi":"10.1142/s0129156424400032","DOIUrl":"https://doi.org/10.1142/s0129156424400032","url":null,"abstract":"Due to the limitations of imaging equipment and image transmission conditions on daily image acquisition, the images acquired are usually low-resolution images, and it will cost a lot of time and economic costs to increase image resolution by upgrading hardware equipment. In this paper, we propose an image super-resolution reconstruction algorithm based on spatio-temporal-dependent residual network MSRN, which fuses multiple features. The algorithm uses the surface feature extraction module to extract the input features of the image, and then uses the deep residual aggregation module to adaptively learn the deep features, and then fuses multiple features and learns the global residual. Finally, the high-resolution image is obtained through the up-sampling module and the reconstruction module. In the model structure, different convolution kernels and jump connections are used to extract more high-frequency information, and spatio-temporal attention mechanism is introduced to focus on more image details. The experimental results show that compared with SRGAN, VDSR and Laplacian Pyramid SRN, the proposed algorithm finally achieves better reconstruction effect, and the image texture details are clearer under different scaling factors. In objective evaluation, the peak signal-to-noise ratio (PSNR) and structure similarity (SSIM) of the proposed algorithm are improved compared with SRGAN.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139604097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Data-Driven Detection of Video Forgery for Secured Microcontrollers: Dataset and Method 数据驱动的安全微控制器视频伪造检测：数据集和方法

International Journal of High Speed Electronics and Systems Pub Date : 2024-01-23 DOI: 10.1142/s0129156424400044

Ran Li, Juan Dai

引用次数: 0

Design of Low Power Analog/RF Signal Processing Circuits Using 22 nm Silicon-on-Insulator Schottky Barrier Nano-Wire MOSFET 使用 22 纳米硅绝缘体肖特基势垒纳米线 MOSFET 设计低功耗模拟/射频信号处理电路

International Journal of High Speed Electronics and Systems Pub Date : 2024-01-23 DOI: 10.1142/s0129156424500034

Jitender Kumar, A. N. Mahajan, S. Deswal, Amit Saxena, R. S. Gupta

引用次数: 0

A Hybrid Optimization-Based Artificial Neural Network Model for Wireless Power Transfer in Electric Vehicles 基于优化的混合人工神经网络模型用于电动汽车的无线电力传输

International Journal of High Speed Electronics and Systems Pub Date : 2023-12-09 DOI: 10.1142/s0129156424500022

Pranjal Jog, R. K. Kumawat

{"title":"A Hybrid Optimization-Based Artificial Neural Network Model for Wireless Power Transfer in Electric Vehicles","authors":"Pranjal Jog, R. K. Kumawat","doi":"10.1142/s0129156424500022","DOIUrl":"https://doi.org/10.1142/s0129156424500022","url":null,"abstract":"Electric Vehicles (EVs) are powered by a battery mounted in the vehicle, which powers the motor and drives the wheels. Most commercial EVs can be charged by plugging them into a charging station. Such conductive recharging has various drawbacks, including physical plugging of the cable, safety concerns, and charging time. Manually charging EVs might be dangerous due to the chance of an electric spark or disaster. Advances in Wireless Power Transfer (WPT) demonstrate the capacity to transfer significant amounts of electricity over short and medium-range distances. The ultimate purpose of this paper is to improve the efficacy of electric car wireless charging systems. Here, a hybrid optimization-based Artificial Neural Network (ANN) model is applied to improve the efficacy of the WPT model in EVs. To optimize the weights of the ANN classifier, a hybrid approach termed as Grasshopper-Assisted Elephant Herd Optimization (GA-EHO) method is proposed. The GA-EHO is derived through the hybridization of Elephant Herd Optimization (EHO) Algorithm and the Grasshopper Optimization Algorithm (GOA) techniques. Finally, the experimental study reveals that at 70% learning rate, the proposed ANN system achieves a minimal MSE value of 0.0528, which is lower than other current classifiers, such as SVM, LSTM, and CNN.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138983080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ultra-Short Pulse-Train Generation of 30-GHz Repetition Rate Using Rational Harmonic Mode Locking and Nonlinear Polarization Rotation 利用有理谐波锁模和非线性极化旋转产生重复频率为30GHz的超短脉冲串

International Journal of High Speed Electronics and Systems Pub Date : 2023-07-20 DOI: 10.1142/s0129156423500246

A. F. M. Moshiur Rahman, S. Fan, N. Dutta

引用次数: 0

Hybrid Mode-Locked Fiber Ring Laser Using Graphene Saturable Absorbers to Generate 20 and 50-GHz Pulse Trains 使用石墨烯可饱和吸收材料产生20和50GHz脉冲串的混合锁模光纤环形激光器

International Journal of High Speed Electronics and Systems Pub Date : 2023-07-20 DOI: 10.1142/s0129156423500106

A. Rahman, S. Fan, N. Dutta

引用次数: 0

Heating Effects on Nanofabricated Plasmonic Dimers with Interconnects 纳米互连等离子体二聚体的加热效应

International Journal of High Speed Electronics and Systems Pub Date : 2023-07-20 DOI: 10.1142/s0129156423500040

R. Raman, J. Grasso, B. Willis

{"title":"Heating Effects on Nanofabricated Plasmonic Dimers with Interconnects","authors":"R. Raman, J. Grasso, B. Willis","doi":"10.1142/s0129156423500040","DOIUrl":"https://doi.org/10.1142/s0129156423500040","url":null,"abstract":"Plasmonic nanostructures with electrical connections have potential applications as new electro-optic devices due to their strong light–matter interactions. Plasmonic dimers with nanogaps between adjacent nanostructures are especially good at enhancing local electromagnetic (EM) fields at resonance for improved performance. In this study, we use optical extinction measurements and high-resolution electron microscopy imaging to investigate the thermal stability of electrically interconnected plasmonic dimers and their optical and morphological properties. Experimental measurements and finite difference time domain (FDTD) simulations are combined to characterize temperature effects on the plasmonic properties of large arrays of Au nanostructures on glass substrates. Experiments show continuous blue shifts of extinction peaks for heating up to 210°C. Microscopy measurements reveal these peak shifts are due to morphological changes that shrink nanorods and increase nanogap distances. Simulations of the nanostructures before and after heating find good agreement with experiments. Results show that plasmonic properties are maintained after thermal processing, but peak shifts need to be considered for device design.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47904814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Threshold Inverter Quantizer (TIQ)-Based 2-Bit Comparator Using Spatial Wavefunction Switched (SWS) FET Inverters 基于阈值反相器量化器（TIQ）的空间波函数开关FET反相器2位比较器

International Journal of High Speed Electronics and Systems Pub Date : 2023-07-20 DOI: 10.1142/s0129156423500258

W. Alamoudi, B. Saman, R. Gudlavalleti, A. Almalki, J. Chandy, E. Heller, F. Jain

{"title":"Threshold Inverter Quantizer (TIQ)-Based 2-Bit Comparator Using Spatial Wavefunction Switched (SWS) FET Inverters","authors":"W. Alamoudi, B. Saman, R. Gudlavalleti, A. Almalki, J. Chandy, E. Heller, F. Jain","doi":"10.1142/s0129156423500258","DOIUrl":"https://doi.org/10.1142/s0129156423500258","url":null,"abstract":"A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45698744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Filtration Methods for Microplastic Removal in Wastewater Streams — A Review 去除废水流中微塑料的过滤方法综述

International Journal of High Speed Electronics and Systems Pub Date : 2023-07-20 DOI: 10.1142/s0129156423500192

U. Salahuddin, J. Sun, Chun Jiang Zhu, P. Gao

引用次数: 0

Propagation Delay and Power Dissipation Analysis for a 2-Bit SRAM Using Multi-State SWS Inverter 基于多态SWS逆变器的2位SRAM传输延迟和功耗分析

International Journal of High Speed Electronics and Systems Pub Date : 2023-07-20 DOI: 10.1142/s0129156423500234

A. Husawi, R. Gudlavalleti, B. Saman, A. Almalki, J. Chandy, E. Heller, F. Jain

{"title":"Propagation Delay and Power Dissipation Analysis for a 2-Bit SRAM Using Multi-State SWS Inverter","authors":"A. Husawi, R. Gudlavalleti, B. Saman, A. Almalki, J. Chandy, E. Heller, F. Jain","doi":"10.1142/s0129156423500234","DOIUrl":"https://doi.org/10.1142/s0129156423500234","url":null,"abstract":"This paper presents a study on the propagation delay and power dissipation of a 2-bit static random-access memory (SRAM) with two cross-coupled multi-state spatial wave function switching (SWS) CMOS inverters. The proposed SRAM design utilizes the advantages of the CMOS-SWS inverter, such as its small area, low power consumption, and high speed. The 2-bit SRAM circuit simulations were carried out in Cadence to analyze the power dissipation and propagation delay. An Analog Behavioral Model (ABM) and the Berkeley Short-channel IGFET Model (BSIM4.6) in 0.18-μm technology were combined to create this model. The analysis of the propagation delay shows that the multi-state CMOS-SWS SRAM significantly reduces the delay compared to other multi-state 6T SRAM memories. Additionally, the analysis of the power dissipation shows that the multi-state SWS-SRAM is comparable to conventional SRAMs. These results demonstrate the potential of multi-state SWS-SRAM for improving the performance of memory circuits and provide valuable insights for future design optimization.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43830769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0