2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)最新文献_第2页

Addiguration: Exploring configuration behavior of Spartan-3 devices 配置:探索Spartan-3设备的配置行为

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI: 10.1109/ReCoSoC.2013.6581543

M. Dreschmann, O. Sander, Alexander Klimm, Christoph Roth, J. Becker

引用次数: 0

SoC performance evaluation with ArchC and TLM-2.0 基于ArchC和TLM-2.0的SoC性能评估

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI: 10.1109/ReCoSoC.2013.6581521

Jörg Walter, Jörg Lenhardt, W. Schiffmann

引用次数: 1

A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m 基于可编程fpga的F2m双线性对密码处理器

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI: 10.1109/ReCoSoC.2013.6581528

Eduardo Cuevas-Farfan, M. Morales-Sandoval, R. Cumplido, C. F. Uribe, I. Algredo-Badillo

{"title":"A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m","authors":"Eduardo Cuevas-Farfan, M. Morales-Sandoval, R. Cumplido, C. F. Uribe, I. Algredo-Badillo","doi":"10.1109/ReCoSoC.2013.6581528","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2013.6581528","url":null,"abstract":"Bilinear pairings over elliptic curves are an emerging research field in cryptography. First cryptographic protocols based on bilinear pairings were proposed by the year 2000 and currently they are not standardized yet. The computation of bilinear pairings relies on arithmetic over finite fields. In the literature, several works have focused in the design of custom hardware architectures for efficient implementation of this arithmetic, but in a non-standardized environment a flexible design is prefered in order to support changes in the specifications. This paper presents the design and implementation of a novel programmable cryptoprocessor for computing bilinear pairings over binary fields in FPGA, which is able to support different algorithms and corresponding parameters as the elliptic curve, the tower field and the distortion map. The results show that high flexibility is achieved by the proposed cryptoprocessor at a competitive timing and area usage, when it is compared to custom designs for pairings defined over singular/supersingular elliptic curves at a 128-bit security level.","PeriodicalId":354964,"journal":{"name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127215673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An FPGA design and implementation framework combined with commercial VLSI CADs 结合商用VLSI cad的FPGA设计与实现框架

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI: 10.1109/ReCoSoC.2013.6581534

Qian Zhao, M. Amagasaki, M. Iida, M. Kuga, T. Sueyoshi

引用次数: 0

An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture 为灵活的多asip涡轮解码器架构提供高效的片上配置基础设施

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI: 10.1109/ReCoSoC.2013.6581518

Vianney Lapôtre, M. Hübner, G. Gogniat, Purushotham Murugappa, A. Baghdadi, J. Diguet

引用次数: 0

Towards a Configurable Many-core Accelerator for FPGA-based embedded systems 面向fpga嵌入式系统的可配置多核加速器

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI: 10.1109/ReCoSoC.2013.6581548

Marco Ramírez, M. Daneshtalab, P. Liljeberg, J. Plosila

引用次数: 1

Reconciling application power control and operating systems for optimal power and performance 协调应用电源控制和操作系统，以获得最佳电源和性能

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI: 10.1109/ReCoSoC.2013.6581539

Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, K. Kimura, H. Kasahara

{"title":"Reconciling application power control and operating systems for optimal power and performance","authors":"Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, K. Kimura, H. Kasahara","doi":"10.1109/ReCoSoC.2013.6581539","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2013.6581539","url":null,"abstract":"In the age of dark silicon on-chip power control is a necessity. Upcoming and state of the art embedded- and cloud computer system-on-chips (SoCs) already provide interfaces for fine grained power control. Sometimes both: core- and interconnect-voltage and frequency can be scaled for example. To further reduce power consumption SoCs often have specialized accelerators. Due to the rising specialization of hard- and software general purpose operating systems require changes to exploit the power saving opportunities provided by the hardware. However, they lack detailed hardware- and application-level-information. Application-level power control in turn is still very uncommon and difficult to realize. Now a days vendors of mobile devices are forced to tweak and patch system-level software to enhance the power efficiency of each individual product. This manual process is time consuming and must be re-iterated for each new product. In this paper we explore the opportunities and challenges of automatic application- level power control using compilers.","PeriodicalId":354964,"journal":{"name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"1998 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128239487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

On a FPGA-based method for authentication using Edwards curves 基于fpga的爱德华兹曲线认证方法研究

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI: 10.1109/ReCoSoC.2013.6581530

André Himmighofen, Bernhard Jungk, S. Reith

引用次数: 3

A new model for estimating bit error probabilities of Ring-Oscillator PUFs 环形振荡器puf误码概率估计的新模型

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI: 10.1109/ReCoSoC.2013.6581531

Matthias Hiller, G. Sigl, Michael Pehl

{"title":"A new model for estimating bit error probabilities of Ring-Oscillator PUFs","authors":"Matthias Hiller, G. Sigl, Michael Pehl","doi":"10.1109/ReCoSoC.2013.6581531","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2013.6581531","url":null,"abstract":"Embedded systems carry and process more and more sensitive information in untrusted environments, where an attacker can wiretap the external communication and also has unlimited physical access to the device. Cryptography protects systems against many of the threats and relies on the security of the cryptographic keys inside the system. Physical Unclonable Functions (PUFs) measure manufacturing variations inside integrated circuits, for example FPGAs, to generate a unique secret PUF response inside each device. Similar to deriving a biometric pattern from human features, the individual pattern inside an FPGA differs slightly from measurement to measurement. From these measurements, the PUF response is generated to derive a secure and reliable cryptographic key. The Ring-Oscillator (RO) PUF is a popular PUF type because of its high randomness and reliability. Frequencies of ROs are compared pairwise to derive one secret bit. So far, the reliability of RO PUFs was evaluated by counting bit flips in measured PUF responses. This work analyzes the distribution of frequency measurements to derive the behavior of the PUF. Analyzing the frequency distributions gives a more precise estimation of the PUF bit error rates than measuring the bit errors after the comparison of two oscillator frequencies. The evaluation of publicly available real world empirical FPGA data has shown that most error probabilities of RO PUF responses are so low that they cannot be measured in feasible time. For almost 200 evaluated FPGAs, more than 70% of the PUF outputs on every FPGA have bit error probabilities under 10-20. We can even ensure this error probability for over 60% of the PUF outputs after a practicable number of frequency measurements with a confidence of 99.9%. Index Terms-Physical Unclonable Functions (PUFs), Ring Oscillator PUF, FPGA, Statistics.","PeriodicalId":354964,"journal":{"name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121795116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Centralized traffic monitoring for online-resizable clusters in Networks-on-Chip 片上网络中在线可调整大小集群的集中流量监控

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI: 10.1109/ReCoSoC.2013.6581523

Philipp Gorski, D. Timmermann

{"title":"Centralized traffic monitoring for online-resizable clusters in Networks-on-Chip","authors":"Philipp Gorski, D. Timmermann","doi":"10.1109/ReCoSoC.2013.6581523","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2013.6581523","url":null,"abstract":"Runtime-based traffic monitoring is one of the most essential system services for modern many-core platforms. It ensures self-awareness of the current system load and enables other runtime mechanisms, like application mapping and adaptive routing, to optimize workload operations. While Networks-on-Chip introduced a scalable and massively parallel communication infrastructure for the growing number of on-chip resources, scalable traffic monitoring becomes a key concern. A high degree of runtime adaptivity at different system layers comes with the costs that monitored system states need to be available at different locations, scopes and resolutions. Furthermore, many-core systems with hundreds of resources will be less single purpose and run workloads composed of various application domains, traffic and timing characteristics. Thus, the monitoring operations should be adaptive to consider this variability and provide customizable behavior. In the work at hand, a runtime configurable and cluster-based traffic monitoring is proposed. Our experiments show that in maximum 2% hardware overhead per tile in an 8×8 NoC is needed to enable online resizable clustering of up to 64 IP cores, centralized traffic monitoring of all path and link loads inside these clusters at resolutions of 1%, and configurable monitoring timing adjustment in a range of 103 to 105 clock cycles.","PeriodicalId":354964,"journal":{"name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117263565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7