基于ArchC和TLM-2.0的SoC性能评估

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI:10.1109/ReCoSoC.2013.6581521

Jörg Walter, Jörg Lenhardt, W. Schiffmann

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引用次数: 1

摘要

ArchC是一种体系结构描述语言，提供指令集级仿真和二进制工具链生成。它基于SystemC，可以使用事务级建模(TLM)与其他SystemC组件通信。在本文中，我们介绍了ArchC的升级，它允许使用TLM-2.0，并使其可用于定时模拟。这些扩展使围绕ArchC处理器模型构建的完整片上系统设计的性能评估成为可能。作为概念验证，我们研究了各种tlm连接的内存层次结构。我们概述了模型设计人员如何使用快速功能仿真和慢时间仿真的组合来确定给定工作负载的最佳系统架构。

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SoC performance evaluation with ArchC and TLM-2.0

ArchC is an architecture description language that provides instruction set level simulation and binary tool chain generation. It is based on SystemC and can communicate with other SystemC components using transaction level modeling (TLM). In this article we present an upgrade of ArchC that allows TLM-2.0 usage and makes it available in timed simulations. These extensions enable performance evaluation of complete System-on-Chip designs built around an ArchC processor model. As a proof-of-concept, we examine various TLM-connected memory hierarchies. We outline how model designers can use a combination of fast functional simulation and slow timed simulation to determine an optimal system architecture for a given workload.

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2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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