面向fpga嵌入式系统的可配置多核加速器

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2013-07-10 DOI:10.1109/ReCoSoC.2013.6581548

Marco Ramírez, M. Daneshtalab, P. Liljeberg, J. Plosila

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引用次数: 1

摘要

硬件加速器将系统的通用处理器从非常需要计算的任务中释放出来。这项工作提出了一种可配置的多核加速器，用于基于fpga的系统，命名为CoMA。它的体系结构结合了由NoC连接的一系列处理核心，以及基于AXI协议的I/O接口。CoMA为设计人员提供了一个系统抽象层，便于任务划分和外设访问。通过仿真验证了该I/O接口的实现，并在FPGA上进行了合成。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Towards a Configurable Many-core Accelerator for FPGA-based embedded systems

Hardware accelerators release the general purpose processor of a system from very compute-demanding tasks. This work presents a Configurable Many-core Accelerator for FPGA-based systems, named CoMA. Its architecture combines an array of processing cores interconnected by an NoC, with an I/O interface based on the AXI protocol. CoMA provides the designer with a system abstraction layer that facilitates task partitioning and peripheral access. The implementation of the I/O interface was verified through simulation, and synthesized for an FPGA.

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2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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