2011 IEEE 29th International Conference on Computer Design (ICCD)最新文献_第8页

Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA 在FPGA上实现IEEE-754四倍精度基本功能的专用VLIW架构

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081400

Yuanwu Lei, Y. Dou, Li Shen, Jie Zhou, Song Guo

{"title":"Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA","authors":"Yuanwu Lei, Y. Dou, Li Shen, Jie Zhou, Song Guo","doi":"10.1109/ICCD.2011.6081400","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081400","url":null,"abstract":"This work explores the feasibility to implement IEEE-754-2008 standard quadruple precision (Quad) elementary functions on recent FPGAs with plenty of embedded memories and DSP blocks. First, we analysis the implementation algorithm of Quad elementary functions in detail. Then, we present a special-purpose Very Large Instruction Word (VLIW) architecture for Quad elementary function (QE-Processor). The proposed processor uses a unified hardware structure, equipped with multiple basic arithmetic units, to implement various Quad algebraic and transcendental functions, in which several tradeoffs between latency and resource usage are carefully planned to avoid unbalanced resource utilization. The performance is improved through the explicitly parallel technology of custom VLIW instruction. Finally, we create a prototype of QE-Processor into Xilinx Virtex-5 and Virtex-6 FPGA chips. The experimental results show that our design can guarantee that the percentage of correct rounding is more than 99.9%. Moreover, the FPGA implementation on Virtex-6 XC6VLX760-2FF1760 FPGA, running at 220 MHz, outperforms the parallel software approach based on OpenMP running on an Intel Xeon E5620 CPU at 2.40GHz by a factor of 13X-20X for special function applications in Boost library.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116203896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Functional correctness for CMP interconnects CMP互连的功能正确性

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081423

Rawan Abdel-Khalek, Ritesh Parikh, A. DeOrio, V. Bertacco

{"title":"Functional correctness for CMP interconnects","authors":"Rawan Abdel-Khalek, Ritesh Parikh, A. DeOrio, V. Bertacco","doi":"10.1109/ICCD.2011.6081423","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081423","url":null,"abstract":"As transistor counts continue to scale, modern designs are transitioning towards large chip multi-processors (CMPs). In order to match the advancing performance of CMPs, on-chip interconnects are becoming increasingly complex, commonly deploying advanced network-on-chip (NoC) structures. Ensuring the correct operation of these system-level infrastructures has become increasingly problematic and, in order to avoid the potential for functional design errors manifesting into the final product, there is a need for mechanisms to safeguard communication integrity at runtime. In this paper, we propose SafeNoC, an end-to-end error detection and recovery solution to ensure the functional correctness of CMP interconnects. SafeNoC augments the existing interconnect with a simple, lightweight checker network that is guaranteed to deliver messages correctly. For each data message sent over the primary NoC, a look-ahead signature is transmitted over the checker network and is used to detect errors in the corresponding data message. If a functional communication bug is detected, a novel recovery algorithm reconstructs the data that was in flight at the time of the error occurrence, ensuring that it reaches the intended destination. In our experiments, we found that SafeNoC can recover from a wide variety of errors, with almost no performance impact in the absence of errors. A lightweight solution, SafeNoC occupies a 2.41% area overhead in a 64-core CMP, 7× smaller than common retransmission-based approaches.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121297368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Impact and optimization of lithography-aware regular layout in digital circuit design 光刻感知规则布局在数字电路设计中的影响与优化

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081409

V. D. Bem, P. Butzen, F. Marranghello, A. Reis, R. Ribas

引用次数: 10

Path aware event scheduler in HoldAdvisor for fixing min timing violations 在HoldAdvisor中的路径感知事件调度程序，用于修复最小的时间违规

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081378

T.-Y. Xiao, Harshinder Bagga, George J. Chen, Richard Cheung, Raghu Pattipati

引用次数: 6

Memory coherence in the age of multicores 多核时代的存储器一致性

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081367

Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, S. Devadas

引用次数: 22

Sequential hardware Trojan: Side-channel aware design and placement 顺序硬件木马:侧通道感知设计和放置

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081413

Xinmu Wang, S. Narasimhan, A. Krishna, T. Mal-Sarkar, S. Bhunia

引用次数: 50

Thread-aware dynamic shared cache compression in multi-core processors 多核处理器中线程感知的动态共享缓存压缩

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081388

Yuejian Xie, G. Loh

{"title":"Thread-aware dynamic shared cache compression in multi-core processors","authors":"Yuejian Xie, G. Loh","doi":"10.1109/ICCD.2011.6081388","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081388","url":null,"abstract":"When a program's working set exceeds the size of its last-level cache, performance may suffer due to the resulting off-chip memory accesses. Cache compression can increase the effective cache size and therefore reduce misses, but compression also introduces access latency because cache lines need to be decompressed before using. Cache compression can help some applications but hurt others, depending on the working set of the currently running program and the potential compression ratio. Previous studies proposed techniques to dynamically enable compression to adapt to the program's behavior. In the context of shared caches in multi-cores, the compression decision becomes more interesting because the cache is shared by multiple applications that may benefit differently from a compressed cache. This paper proposes Thread-Aware Dynamic Cache Compression (TADCC) to make better compression decisions on a per-thread basis. Access Time Tracker (ATT) can estimate the access latencies of different compression decisions. The ATT is supported by a Decision Switching Filter (DSF) that provides stability and robustness. As a result, TADCC outperforms a previously proposed adaptive cache compression technique by 8% on average and as much as 17%.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126572469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Towards a tool for implementing delay-free ECC in embedded memories 在嵌入式存储器中实现无延迟ECC的工具

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081440

Thierry Bonnoit, M. Nicolaidis, N. Zergainoh

引用次数: 2

A dynamic and distributed TDM slot-scheduling protocol for QoS-oriented Networks-on-Chip 面向qos的片上网络的动态分布式TDM时隙调度协议

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081372

Nicola Concer, Andrea Vesco, R. Scopigno, L. Carloni

{"title":"A dynamic and distributed TDM slot-scheduling protocol for QoS-oriented Networks-on-Chip","authors":"Nicola Concer, Andrea Vesco, R. Scopigno, L. Carloni","doi":"10.1109/ICCD.2011.6081372","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081372","url":null,"abstract":"We propose a run-time distributed and dynamic scheduling protocol for Quality-of-Service oriented Networks-on-Chip implementing Time Division Multiplexing of the channels. Our protocol automatically allocates the channel time-slots according to the specific routing algorithm implemented by the routers and the communication requirements of the applications currently executing. We present a theoretical analysis to model the protocol performance based on the traffic characteristics and to optimize the configuration of the NoC architecture which we propose to implement the protocol. This architecture relies on two independent and parallel networks: the first network transfers QoS-demanding data while the second is used to control the first and for best-effort traffic. System-level simulations demonstrate the effectiveness of this approach by showing that the runtime-generated reservation requests for QoS-demanding data are accepted by the NoC with very low blocking probability and that once a reservation has been established the requested latency and throughput guarantees are consistently met.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116882592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Is single-scheme Trojan prevention sufficient? 单方案木马防护是否足够?

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-01 DOI: 10.1109/ICCD.2011.6081415

Yier Jin, Y. Makris

引用次数: 5