2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)最新文献_第2页

Verification Driven Formal Architecture and Microarchitecture Modeling 验证驱动的正式体系结构和微体系结构建模

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) Pub Date : 2007-05-30 DOI: 10.1109/MEMCOD.2007.371235

Yogesh S. Mahajan, C. Chan, A. A. Bayazit, S. Malik, W. Qin

引用次数: 14

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults 结合多值逻辑的sat ATPG路径延迟故障处理

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) Pub Date : 2007-05-30 DOI: 10.1109/MEMCOD.2007.371226

Stephan Eggersglüß, G. Fey, R. Drechsler, Andreas Glowatz, F. Hapke, J. Schlöffel

引用次数: 11

Multi-Level Assertion-Based Design 多级基于断言的设计

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) Pub Date : 2007-05-30 DOI: 10.1109/MEMCOD.2007.371244

H. Eveking, Martin Braun, Martin Schickel, Martin Schweikert, Volker Nimbler

引用次数: 7

Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA 基于Xilinx FPGA的矩阵乘法硬件加速

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) Pub Date : 2007-05-30 DOI: 10.1109/MEMCOD.2007.371239

Nirav H. Dave, Kermin Fleming, Myron King, Michael Pellauer, M. Vijayaraghavan

引用次数: 50

Proving What Programs Do Not 证明程序不能做什么

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) Pub Date : 2007-05-30 DOI: 10.1109/MEMCOD.2007.371233

B. Meyer

引用次数: 0

Type Inference for IP Composition IP组合的类型推断

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) Pub Date : 2007-05-30 DOI: 10.1109/MEMCOD.2007.371248

D. Mathaikutty, S. Shukla

引用次数: 2

Easier and More Informative Vacuity Checks 更容易和更有信息的真空度检查

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) Pub Date : 2007-05-30 DOI: 10.1109/MEMCOD.2007.371225

Hana Chockler, O. Strichman

{"title":"Easier and More Informative Vacuity Checks","authors":"Hana Chockler, O. Strichman","doi":"10.1109/MEMCOD.2007.371225","DOIUrl":"https://doi.org/10.1109/MEMCOD.2007.371225","url":null,"abstract":"In formal verification, we verify that a system is correct with respect to a specification. Cases like antecedent failure can make a successful pass of the verification procedure meaningless. Vacuity detection can signal such \"meaningless\" passes of the specification, and indeed vacuity checks are now a standard component in many commercial model checkers. We address two dimensions of vacuity: the computational effort and the information that is given to the user. As for the first dimension, we present several preliminary vacuity checks that can be done without the design itself, which implies that some information can be found with a significantly smaller effort. As for the second dimension, we present algorithms for deriving three types of information that are not provided by standard vacuity checks, assuming M = phi for a model M and property phi: a) behaviors that are possibly missing from M (or wrongly restricted by the environment) b) the largest subset of occurrences of literals in phi that can be replaced with false simultaneously without falsifying phi in M, and finally c) the degree of responsibility of each occurrence of a literal in phi to its satisfaction in the model M, which can be seen as a fine-grain form of vacuity. The complexity of each of these problems is proven. Overall this extra information can lead to tighter specifications and more guidance for finding errors.","PeriodicalId":345459,"journal":{"name":"2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)","volume":"743 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122959884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Software/Hardware Engineering with the Parallel Object-Oriented Specification Language 软件/硬件工程与并行面向对象规范语言

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) Pub Date : 2007-05-30 DOI: 10.1109/MEMCOD.2007.371231

B. Theelen, O. Florescu, M. Geilen, Jinfeng Huang, P. V. D. Putten, J. Voeten

{"title":"Software/Hardware Engineering with the Parallel Object-Oriented Specification Language","authors":"B. Theelen, O. Florescu, M. Geilen, Jinfeng Huang, P. V. D. Putten, J. Voeten","doi":"10.1109/MEMCOD.2007.371231","DOIUrl":"https://doi.org/10.1109/MEMCOD.2007.371231","url":null,"abstract":"The complexity of designing hardware/software systems motivates research on frameworks that structure and automate the design process. Such design methodologies reduce the risk of expensive design-implementation iterations by assisting designers in constructing models. Software/hardware engineering (SHE) is a general-purpose system-level design methodology that supports analysing both functional correctness and performance properties. SHE combines the Unified Modelling Language with the parallel object-oriented specification language to specify models. The designer is assisted in constructing models using these languages and applying the analysis techniques with various guidelines and modelling patterns. A key feature of SHE is its foundation on formal methods, which ensures that the obtained analysis results are unambiguous. SHE also includes guidelines and techniques for automatic synthesis of real-time control software. This is again based on formal methods to ensure that properties in a model (including real-time properties) are preserved by the software realisation. Finally, to enable an effective and efficient application of the modelling languages as well as the analysis and synthesis techniques, SHE is accompanied with a set of user-friendly tools. This paper gives an overview of SHE, thereby briefly touching upon the underlying mathematical foundation of the analysis and synthesis techniques as well as upon some open issues that require further research.","PeriodicalId":345459,"journal":{"name":"2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130908507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 100

Scheduling as Rule Composition 作为规则组合的调度

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) Pub Date : 2007-05-30 DOI: 10.1109/MEMCOD.2007.371249

Nirav H. Dave, Arvind, Michael Pellauer

{"title":"Scheduling as Rule Composition","authors":"Nirav H. Dave, Arvind, Michael Pellauer","doi":"10.1109/MEMCOD.2007.371249","DOIUrl":"https://doi.org/10.1109/MEMCOD.2007.371249","url":null,"abstract":"Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware as a collection of stateful elements (e.g., registers, memories) and describes its behavior using rules, or Guarded Atomic Actions which modify these elements. All legal behaviors of a Bluespec program can be explained in terms of rules being applied in some sequence. Scheduling is the process of selecting which rules to execute in parallel while maintaining this semantic invariant. The scheduling decision can have a large impact on critical design properties such as pipeline concurrency and clock frequency. What constitutes a good schedule of en depends upon the application and requires the designer's input. In this paper we introduce BTRS, the kernel language for Bluespec and use it to explore the task of scheduling. We view scheduling as the process of restricting a Bluespec design's non-deterministic behavior to be deterministic. We define a small set of scheduling operators whose semantics are expressed in terms of rule composition. We show how to represent the schedules generated by the Bluespec compiler using these compositions. More importantly, our scheduling primitives open a large class of new schedules which are needed for microarchitectural explorations.","PeriodicalId":345459,"journal":{"name":"2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)","volume":"80 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120877751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

Temporal Refinement Using SMT and Model Checking with an Application to Physical-Layer Protocols 使用SMT和模型检验的时间精化与物理层协议的应用

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) Pub Date : 2007-05-30 DOI: 10.1109/MEMCOD.2007.371227

Geoffrey M. Brown, Lee Pike

引用次数: 6