N. Bombieri, F. Fummi, G. Pravadelli, Joao Marques-Silva
{"title":"Towards Equivalence Checking Between TLM and RTL Models","authors":"N. Bombieri, F. Fummi, G. Pravadelli, Joao Marques-Silva","doi":"10.1109/MEMCOD.2007.371236","DOIUrl":"https://doi.org/10.1109/MEMCOD.2007.371236","url":null,"abstract":"The always increasing complexity of digital system is overcome in design flows based on transaction level modeling (TLM) by designing and verifying the system at different abstraction levels. The design implementation starts from a TLM high-level description and, following a top- down approach, it is refined towards a corresponding RTL model. However, the bottom-up approach is also adopted in the design flow when already existing RTL IPs are abstracted to be reused into the TLM system. In this context, proving the equivalence between a model and its refined or abstracted version is still an open problem. In fact, traditional equivalence definitions and formal equivalence checking methodologies presented in the literature cannot be applied due to the very different internal characteristics of the models, including structure organization and timing. Targeting this topic, the paper presents a formal definition of equivalence based on events, and then, it shows how such a definition can be used for proving the equivalence in the RTL vs. TLM context, without requiring timing or structural similarities between the modules to be compared. Finally, the paper presents a practical use of the proposed theory, by proving the correctness of a methodology that automatically abstracts RTL IPs towards TLM implementations.","PeriodicalId":345459,"journal":{"name":"2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122001124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Executable Analysis using Abstract Interpretation with Circular Linear Progressions","authors":"Rathijit Sen, Y. Srikant","doi":"10.1109/MEMCOD.2007.371251","DOIUrl":"https://doi.org/10.1109/MEMCOD.2007.371251","url":null,"abstract":"We propose a new abstract domain for static analysis of executable code. Concrete states are abstracted using circular linear progressions (CLPs). CLPs model computations using a finite word length as is seen in any real life processor. The finite abstraction allows handling overflow scenarios in a natural and straight-forward manner. Abstract transfer functions have been defined for a wide range of operations which makes this domain easily applicable for analyzing code for a wide range of ISAs. CLPs combine the scalability of interval domains with the discreteness of linear congruence domains. We also present a novel, lightweight method to track linear equality relations between static objects that is used by the analysis to improve precision. The analysis is efficient, the total space and time overhead being quadratic in the number of static objects being tracked.","PeriodicalId":345459,"journal":{"name":"2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122672870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MEMOCODE 2007 Co-Design Contest","authors":"F. Brewer, J. Hoe","doi":"10.1109/MEMCOD.2007.371241","DOIUrl":"https://doi.org/10.1109/MEMCOD.2007.371241","url":null,"abstract":"New to the 2007 MEMOCODE conference is the HW/SW Co-Design Contest. Members of the technical and steering committees from MEMOCODE 2006 thought that the co-design practice is distinct from conventional hardware or software design practice. A co-design contest was conceived to help elucidate these issues and to foster greater interest in the design aspects of the MEMOCODE conference. The contest would also serve to showcase advances in co-design tools and methodologies. Below, we describe briefly the development of the contest format and the thinking behind the choices. The actual call-for-participation that appeared on the contest website (http://memocode07.ece.cmu.edu/contest.html) is reproduced in the appendix section.","PeriodicalId":345459,"journal":{"name":"2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130785629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Man Cheuk Ng, M. Vijayaraghavan, Nirav H. Dave, Arvind, Gopal Raghavan, Jamey Hicks
{"title":"From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols","authors":"Man Cheuk Ng, M. Vijayaraghavan, Nirav H. Dave, Arvind, Gopal Raghavan, Jamey Hicks","doi":"10.1109/MEMCOD.2007.371247","DOIUrl":"https://doi.org/10.1109/MEMCOD.2007.371247","url":null,"abstract":"Orthogonal frequency-division multiplexing (OFDM) has become the preferred modulation scheme for both broadband and high bitrate digital wireless protocols because of its spectral efficiency and robustness against multipath interference. Although the components and overall structure of different OFDM protocols are functionally similar, the characteristics of the environment for which a wireless protocol is designed often result in different instantiations of various components. In this paper, we describe how we can instantiate baseband processoring of two different wireless protocols, namely 802.11a and 802.16 in Bluespec from a highly parameterized code for a generic OFDM protocol. Our approach results in highly reusable IP blocks that can dramatically reduce the time-to-market of new OFDM protocols. One advantage of Bluespec over SystemC is that our code is synthesizable into high quality hardware, which we demonstrate via synthesis results. Using a Viterbi decoder we also demonstrate how parameterization can be used to study area-performance tradeoff in the implementation of a module. Furthermore, parameterized modules and modular composition can facilitate implementation-grounded algorithmic exploration in the design of new protocols.","PeriodicalId":345459,"journal":{"name":"2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)","volume":"80 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134445564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Local Causal Reasoning of a Safety-Critical Subway System","authors":"E. Daylight, S. Shukla","doi":"10.1109/MEMCOD.2007.371245","DOIUrl":"https://doi.org/10.1109/MEMCOD.2007.371245","url":null,"abstract":"Translating an informal design intent into a formal specification is an error prone process. A designer may be able to claim that his implementation meets his formal specification. But, in many cases, he cannot confidently claim that his formal specification correctly captures the original design intent. This problem, in our views, is due to global causal reasoning, as we show with LUSTRE for a Subway system. To resolve this lack of confidence, we briefly present our interactive design tool, which forces a designer to reason locally while formally specifying the design intent.","PeriodicalId":345459,"journal":{"name":"2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122627567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}