2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)最新文献

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Unbalanced FIFO sorting for FPGA-based systems 基于fpga系统的非平衡FIFO排序
R. Marcelino, H. Neto, João MP Cardoso
{"title":"Unbalanced FIFO sorting for FPGA-based systems","authors":"R. Marcelino, H. Neto, João MP Cardoso","doi":"10.1109/ICECS.2009.5410898","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410898","url":null,"abstract":"Sorting is an important operation in a myriad of applications. It can contribute substantially to the overall execution time of an application. Dedicated sorting architectures can be used to accelerate applications and/or to reduce energy consumption. In this paper, we propose an efficient sorting unit aiming at accelerating the sort operation in FPGA-based embedded systems. The proposed sorting unit, named Unbalanced FIFO Merge Sorting Unit, is based on a FIFO merger implementation and is easily scalable to handle different data-set sizes. We show results of the proposed sorting unit when isolated and when integrated in a software/hardware solution. When using a Xilinx Virtex-5 SX50T FPGA device, the logic resources for a 32 K-word machine is lower than 1%, and the block RAM usage is about 22%. When compared to a quicksort pure software implementation, our Sorting Unit provides speed-ups from 1.2x to 50x and about 20x when isolated and when integrated in a software/hardware solution, respectively.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115913009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Digital self-aware charge pump calibration technique for frequency synthesizers 频率合成器数字式自感知电荷泵校准技术
Anna M. R. Dixon, M. Ismail, J. Atallah
{"title":"Digital self-aware charge pump calibration technique for frequency synthesizers","authors":"Anna M. R. Dixon, M. Ismail, J. Atallah","doi":"10.1109/ICECS.2009.5410794","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410794","url":null,"abstract":"As radio design complexity increases and features sizes decrease, more innovative solutions are explored to ensure analog circuit designs meet specifications. Digital calibration is an inexpensive and effective solution. A novel digital calibration technique to improve charge pump current mismatch in frequency synthesizers is presented. This method detects the charge pump error by measuring the low pass filter voltage of the system forced to operate at a fixed phase error. A reference table developed from a mathematical model of the system uses the measurement result to produce a digital control word. The digital control word acts on a charge pump array to correct the error. The technique is implemented and tested in Matlab/Simulink for a case study frequency synthesizer. The calibration technique corrects the charge pump current absolute error to within 1.4% of the nominal value. Additionally, the technique is exceptionally effective for correcting the charge pump current mismatch to within 1%.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116238620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A heterogenous approach to symbolic calculations based on structural numbers 基于结构数的符号计算的异质方法
A. Pułka, L. Golly
{"title":"A heterogenous approach to symbolic calculations based on structural numbers","authors":"A. Pułka, L. Golly","doi":"10.1109/ICECS.2009.5410965","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410965","url":null,"abstract":"The paper presents an approach to the problem of automated generation of symbolic functions for complex electronic circuits. The new methodology based on structural numbers combined with graph theory is described. The algorithm is formulated and its implementation as BASE program is presented on examples. Results presenting generation times are given. Comparison to classical techniques and benefits of new approach summarize the contribution.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"13 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115166005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs 一种具有电压缓冲器和零化电阻的高效RNM补偿拓扑,用于大容量负载三级ota
D. Marano, G. Palumbo, S. Pennisi
{"title":"An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs","authors":"D. Marano, G. Palumbo, S. Pennisi","doi":"10.1109/ICECS.2009.5410952","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410952","url":null,"abstract":"This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. Simulations on a three-stage amplifier are carried out and are found to be in excellent agreement with the theoretical analysis, showing a significant improvement of the proposed approach over traditional compensation strategies in terms of small-signal and large-signal performance.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122048143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new horizontal and vertical common subexpression elimination method for multiple constant multiplication 多重常数乘法的横向和纵向公共子表达式消除新方法
Kazunari Kato, Yasuhiro Takahashi, T. Sekine
{"title":"A new horizontal and vertical common subexpression elimination method for multiple constant multiplication","authors":"Kazunari Kato, Yasuhiro Takahashi, T. Sekine","doi":"10.1109/ICECS.2009.5410955","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410955","url":null,"abstract":"The common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the multiple constant multiplication (MCM) blocks. In this paper, we propose a new CSE method using a combining horizontal and vertical technique. The proposed method searches firstly the frequency of higher order horizontal common subexpression, i.e., 3–5 bits, and then searches vertical. Our simulation results show that our method offers a good tradeoff between the implementation cost and the synthesis run-time in comparison with conventional methods.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124268144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Comparison of the WLAN's security functions time consumption WLAN安全功能的时间消耗对比
J. Kadlec, R. Kuchta, R. Vrba
{"title":"Comparison of the WLAN's security functions time consumption","authors":"J. Kadlec, R. Kuchta, R. Vrba","doi":"10.1109/ICECS.2009.5410827","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410827","url":null,"abstract":"Securing of the communication is the key parameter for all wireless networks. WLAN's vulnerability to security threads is solved by several security mechanisms but all of these mechanisms have negative impact to the communication speed and final network performance. Time consumption of different security mechanisms used in wireless networks limits availability for several time-sensitive applications. This paper is focused on the performance tests of the WLAN IEEE 802.11g. New testbed for measuring of the basic network parameters with 10 ns resolution was developed and used for measuring influence of different security level which can be applied in IEEE 802.11g. Three main parameters of network communication in the wireless networks are bandwidth, delay and jitter. Knowing values of those three parameters allows us to decide if the WLAN's parameters are acceptable for using in real-time applications or not. Based on the measured network dynamics we can select which real-time application is suitable for this wireless network. In our measuring we focused on the basic security mechanisms like WEP, WPA and WPA2.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130271517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reduction parasitic capacitance in switching stage RF-CMOS Gilbert mixer for 2.4 GHz application 降低2.4 GHz应用的开关级RF-CMOS吉尔伯特混频器的寄生电容
S. Ziabakhsh, M. Nirouei, A. Saberkari, H. Alavi-Rad
{"title":"Reduction parasitic capacitance in switching stage RF-CMOS Gilbert mixer for 2.4 GHz application","authors":"S. Ziabakhsh, M. Nirouei, A. Saberkari, H. Alavi-Rad","doi":"10.1109/ICECS.2009.5410854","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410854","url":null,"abstract":"This paper presents a topology for Gilbert-cell mixer that leads to a better performance in terms of noise figure, conversion gain and IIP3 at low supply voltage. In this architecture, we have used an extra LC filter for reduction parasitic capacitance noise in switching. Simulation results show the voltage CG of 17.45 dB, NF of 7.04 dB, and IIP3 of −4 dBm.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129676454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Error control in circuit transient analysis 电路暂态分析中的误差控制
A. Gheorghe, F. Constantinescu, M. Nitescu
{"title":"Error control in circuit transient analysis","authors":"A. Gheorghe, F. Constantinescu, M. Nitescu","doi":"10.1109/ICECS.2009.5410972","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410972","url":null,"abstract":"The frequency warping error occurring in transient circuit analysis and the manner to control it are revisited. A new algorithm for the time step choice, based on an energy balance error, is proposed. An example shows that this new algorithm rejects fewer time steps than the SPICE one.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129491077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Sensitivity based parameter reduction for statistical analysis of circuit performance 基于灵敏度的电路性能统计分析参数约简
Ning Chen, Bing Li, Ulf Schlichtmann
{"title":"Sensitivity based parameter reduction for statistical analysis of circuit performance","authors":"Ning Chen, Bing Li, Ulf Schlichtmann","doi":"10.1109/ICECS.2009.5410897","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410897","url":null,"abstract":"If we view a circuit performance such as delay as a function of underlying parameters, e.g. gate length and gate width, the difficulty of performance analysis lies in two aspects: The first one is the high dimension of the parameter space as well as the statistical relationship among these parameters. The second one is the complex mapping between the performance space and the parameter space where commonly no direct analytical form exists and numerical methods are used instead. In this paper, we propose a new method for reducing the dimension of the parameter space while taking the first order sensitivity information into account. Experimental results have verified that the proposed method can achieve lower standard deviation error of the performance in comparison with the traditional method PCA.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131383692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A post-layout optimization method with automatic device type selection for BiCMOS analog circuits 基于器件类型自动选择的BiCMOS模拟电路布局后优化方法
T. Reich, B. Dimov, Christian Lang, V. Boos, E. Hennig
{"title":"A post-layout optimization method with automatic device type selection for BiCMOS analog circuits","authors":"T. Reich, B. Dimov, Christian Lang, V. Boos, E. Hennig","doi":"10.1109/ICECS.2009.5410781","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410781","url":null,"abstract":"In this paper, we present a novel post-layout performance optimization method for BiCMOS analog circuits. Its main feature is a new approach for varying the types of non-scalable devices automatically during the design process using a gradient-based optimizer. This greatly extends the design space for BiCMOS circuits in computer-aided circuit optimization and, consequently, the reuse potential for existing circuit topologies and layouts. The method has been demonstrated successfully on the post-layout optimization of a 0.6-µm BiCMOS high-speed operational amplifier.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127273277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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