S. D’Amico, M. Matteis, F. Grancagnolo, M. Panareo, R. Perrino, G. Chiodini, A. Corvaglia, G. Cocciolo, A. Baschirotto
{"title":"A 0.13µm CMOS VGA for drift chambers","authors":"S. D’Amico, M. Matteis, F. Grancagnolo, M. Panareo, R. Perrino, G. Chiodini, A. Corvaglia, G. Cocciolo, A. Baschirotto","doi":"10.1109/ICECS.2009.5410823","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410823","url":null,"abstract":"The counting of the consecutive ionization clusters in a drift chamber is a very promising technique for particle identification purposes. Up to now the bottleneck for the application of this technique was the possibility of realizing a large number of very-fast read-out channels with reduce power consumption. Typical time separation between each ionization act in a helium-based gas mixture is from a few ns to a few tens of ns. Thus the read-out interface has to be able to process such a high-speed signals. In this paper, the first realization of a CMOS 0.13µm integrated readout circuit, including a fast variable gain amplifier (VGA) with 160MHz bandwidth is designed for the central tracker of a future collider (ILC, super-B). The VGA circuit has been optimized for low power consumption. Moreover, it presents a programmable power consumption (8.4mA, 9.4mA, 10.6mA) according to the gain setting (0dB, 10dB, 20dB). The design issues and the measured performance associated to this architecture are discussed.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123606682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of A CMOS closed-loop system useful for bio-impedance measurements","authors":"A. Yúfera, A. Rueda","doi":"10.1109/ICECS.2009.5410818","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410818","url":null,"abstract":"This paper proposes a method for impedance measurements based on a closed-loop implementation of CMOS circuits. The proposed system has been conceived for alternate current excited systems, performing simultaneously driving and measuring functions thanks to feedback. The system delivers magnitude and phase signals independently, which can be optimized separately. The method can be applied to any kind of load (resistive and capacitive). Design specifications for CMOS circuit blocks and tradeoffs for accuracy and loop stability have been derived. Simulation results for several loads agree with the theory, enabling its application to any impedance measurement problem, in special, to bio-setups including electrodes.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124656436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Asynchronous logic for high variability nano-CMOS","authors":"Alain J. Martin","doi":"10.1109/ICECS.2009.5410925","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410925","url":null,"abstract":"At the nanoscale level, parameter variations in fabricated devices cause extreme variability in delay. Delay variations are also the main issue in subthreshold operation. Consequently, asynchronous logic seems an ideal, and probably unavoidable choice, for the design of digital circuits in nano CMOS or other emerging technologies. This paper examines the robustness of one particular asynchronous logic: quasi-delay insensitive or QDI. We identify the three components of this logic that can be affected by extreme variability: staticizer, isochronic fork, and rings. We show that staticizers can be eliminated, and isochronic forks and rings can be made arbitrarily robust to timing variations.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129631167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mohamed A. Abd El-Ghany, M. El-Moursy, D. Korzec, M. Ismail
{"title":"Power efficient Networks on Chip","authors":"Mohamed A. Abd El-Ghany, M. El-Moursy, D. Korzec, M. Ismail","doi":"10.1109/ICECS.2009.5410930","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410930","url":null,"abstract":"a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduces the power consumption of the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover, the power reduction technique is applied to different NoC architectures. The technique reduces the power consumption of the network by up to 41%. When the power consumption of the whole network including the interswich links and repeaters is taken into account, the overall power consumption is decreased by up to 33% at the maximum operating frequency of the switch. The BFT architecture consumes the minimum power as compared to other NoC architectures.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122357743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Paul-Vahé Cicek, S. Mahdavi, F. Nabki, M. El-Gamal
{"title":"Low actuation voltage silicon carbide RF switches for MEMS above IC","authors":"Paul-Vahé Cicek, S. Mahdavi, F. Nabki, M. El-Gamal","doi":"10.1109/ICECS.2009.5410976","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410976","url":null,"abstract":"This paper presents a CMOS-compatible RF MEMS technology to build low actuation voltage switches. SiC increases the stiffness of the switches to improve reliability and durability. A design methodology is introduced to optimize tradeoffs between important system criteria, i.e., voltage levels, signal performance and switching speed. Simulations are used to evaluate devices designed with the technology.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130223443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Asynchronous design: A promising paradigm for electronic circuits and systems","authors":"E. Yahya, L. Fesquet","doi":"10.1109/ICECS.2009.5411009","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5411009","url":null,"abstract":"This paper introduces the potential benefits of using asynchronous circuits in integrated chips. Their potential advantages in high speed, low power, design of secure chips and enhancing the yield are discussed. In addition, drawbacks of using asynchronous circuits are listed and some practical solutions are proposed.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131715197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rammal Hussein, Olleik Charif, N. Fadlallah, M. Rammal, P. Vaudon
{"title":"General synthesis method for cylindrical antenna arrays for directive and conformal pattern","authors":"Rammal Hussein, Olleik Charif, N. Fadlallah, M. Rammal, P. Vaudon","doi":"10.1109/ICECS.2009.5410892","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410892","url":null,"abstract":"This paper describes a new approach to cylindrical antenna controlled by the excitation (amplitude and phase) to synthesize directive lobe and multilobe patterns, and create adaptive nulls in interference direction and large lobe pattern. The proposed method is based on iterative minimization of a function that incorporates constraints imposed in each direction with respect to excitation (amplitude and phase). To verify the performances of the proposed technique, an 16-element cylindrical antenna has been simulated for various types of beam configurations.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129170325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Haddad, W. Rahajandraibe, Lakhdar Zaïd, O. Frioui, R. Bouchakour
{"title":"Radio frequency tunable polyphase filter design","authors":"F. Haddad, W. Rahajandraibe, Lakhdar Zaïd, O. Frioui, R. Bouchakour","doi":"10.1109/ICECS.2009.5410947","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410947","url":null,"abstract":"Polyphase filters are widely used in radio frequency (RF) receivers either to generate accurate quadrature signals or to reject the image. Analytical modeling of passive polyphase filter suitable for RF front-end applications is exposed. This analytical study has been used to calibrate the optimal values of passive components in order to obtain the maximum image rejection ratio (IRR). Component matching and parasitics reduction techniques have been taken into account. Tunable RC polyphase filter, suitable for multi-standard applications, has been fabricated in 0.13-µm CMOS technology.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129258939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Naoufel Debbabi, S. Chtourou, I. Kammoun, M. Siala
{"title":"Amplify and forward relaying optimization for uplink CDMA communications subject to constant multiple access interference cost","authors":"Naoufel Debbabi, S. Chtourou, I. Kammoun, M. Siala","doi":"10.1109/ICECS.2009.5410834","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410834","url":null,"abstract":"In radio mobile cellular networks, the users located at the cell border are suffering from a bad quality of service (QoS). Cooperative communications is a promising technique that can overcome this weakness by allowing the users to profit from powerful benefits of the spatial diversity. Nevertheless, abstraction is usually made on the impact of the additional multiple access interference inherent to relaying. In this paper, we propose a novel approach that optimizes the system performance of an amplify-and-forward (AF) relaying scheme subject to a constant multiple access interference cost for the uplink CDMA (Code Division Multiple Access) communications. We present a variety of simulation results illustrating the cellular system performance enhancement in term of BER (Bit Error Rate) over direct transmission.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126875054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bo Liu, Francisco V. Fernández, Dimitri de Jonghe, G. Gielen
{"title":"Less expensive and high quality stopping criteria for MC-based analog IC yield optimization","authors":"Bo Liu, Francisco V. Fernández, Dimitri de Jonghe, G. Gielen","doi":"10.1109/ICECS.2009.5410991","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410991","url":null,"abstract":"This paper investigates the stopping criteria for Monte-Carlo (MC)-based yield optimization of analog integrated circuits. Available stopping criteria are briefly reviewed and a new adaptive criterion, called combined global and local improvement (ComImp) is presented. Experimental results show that the proposed stopping criterion has the following two advantages: (1) low risk of early termination before the optimum has been reached with the desired accuracy; (2) less additional function evaluations after the convergence has already been reached.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116129822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}