2007 IEEE International High Level Design Validation and Test Workshop最新文献_第2页

Functional coverage measurements and results in post-Silicon validation of Core™2 duo family Core™2 duo家族的功能覆盖测量和硅后验证结果

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI: 10.1109/HLDVT.2007.4392804

Tommy Bojan, Manuel Aguilar Arreola, Eran Shlomo, Tal Shachar

{"title":"Functional coverage measurements and results in post-Silicon validation of Core™2 duo family","authors":"Tommy Bojan, Manuel Aguilar Arreola, Eran Shlomo, Tal Shachar","doi":"10.1109/HLDVT.2007.4392804","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392804","url":null,"abstract":"Post-Silicon verification is an activity that is still maturing with respect to functional coverage methodologies. The architectural and micro-architectural feedback from silicon can be used to enhance the level of quality of the test suite, and allows monitoring the frequency of interesting micro-architectural events. For the latest Intel Corporation's multi-core processors (Intelreg CoreTM2 Duo processor, Intelreg CoreTM2 Extreme processor, Dual-Core Intelreg Xeonreg processor 5100 series, Intelreg CoreTM2 Duo mobile processor,), validation uses Random Instruction Tool (RIT) generated tests, so the need for coverage increases in importance. There are different methods that are used to understand what the RIT is exercising. In this paper, three efficient orthogonal solution and results vectors are presented: (A) Front-Side-Bus (FSB) Checker and coverage approach exploiting the re-use of mature pre-silicon tools, (B) Extended Execution Trace (EET) mechanism which uses special microcode patches for external tracking of microcode flows, and (C) Performance Monitoring Hardware used to collect frequency coverage of specific internal events. With these approaches, effective Front-Side Bus, microcode and architectural coverage was collected, analyzed and used as feedback for better tuning the RIT generation parameters. These three solutions have been put to practice in projects code named Conroe, Woodcrest, Merom, and Penryn to further improve the quality of test generated by the System Validation's (SV) RIT.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134015134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

Model-driven test generation for system level validation 为系统级验证生成模型驱动的测试

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI: 10.1109/HLDVT.2007.4392792

D. Mathaikutty, Sumit Ahuja, A. Dingankar, S. Shukla

{"title":"Model-driven test generation for system level validation","authors":"D. Mathaikutty, Sumit Ahuja, A. Dingankar, S. Shukla","doi":"10.1109/HLDVT.2007.4392792","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392792","url":null,"abstract":"Functional validation of System Level Models, such as those modeled with SystemC, is an important and complex problem. One of the problems in their functional validation is the test case generation with good coverage and higher potential to find faults in the design. We propose a coverage-directed test generation framework for system level design validation by combining the synchronous language ESTEREL, and its advanced verification capability, with C++ based system level language SystemC. The main contributions of this paper are (i) the integrated framework for model-driven development and validation of system-level designs with a combination of ESTEREL, and SystemC; and (ii) the test generation framework for generating test suites to satisfy traditional coverage metrics such as the statement and branch as well as a complex metric such as modified condition/decision coverage (MCDC) employed in the validation of safety-critical software systems. The framework also generates tests that attain functional coverage using properties specified in a temporal language and assertion-based verification (namely PSL). We demonstrate the methodology with a case study by developing and validating a critical power state machine component that is used for power management in embedded systems.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133070651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

Validating the dependability of embedded systems through fault injection by means of loadable kernel modules 利用可加载内核模块，通过故障注入验证嵌入式系统的可靠性

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI: 10.1109/HLDVT.2007.4392811

M. Murciano, M. Violante

引用次数: 5

An approach for computing the initial state for retimed synchronous sequential circuits 一种计算重定时同步顺序电路初始状态的方法

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI: 10.1109/HLDVT.2007.4392798

N. Chabini, W. Wolf

引用次数: 0

Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production test 面板:统一的方法导致一个无缝发展的测试平台，用于多核设计，验证和生产测试的所有阶段

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI: 10.1109/HLDVT.2007.4392808

Sunil Kakkar, J. Bergeron, B. Bailey, H. Foster, I. Harris

引用次数: 0

Post-silicon verification methodology on Sun’s UItraSPARC T2 Sun的UItraSPARC T2的硅后验证方法

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI: 10.1109/HLDVT.2007.4392784

J. Kumar, Catherine Ahlschlager, P. Isberg

{"title":"Post-silicon verification methodology on Sun’s UItraSPARC T2","authors":"J. Kumar, Catherine Ahlschlager, P. Isberg","doi":"10.1109/HLDVT.2007.4392784","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392784","url":null,"abstract":"In general, considerable time and resources are spent during pre-silicon verification phase to proactively minimize functional issues at first silicon. This is no different on the UltraSPARC T2 - the world's fastest commodity microprocessor. We deployed simulation, formal and emulation technologies coupled with solid methodology to cover all our bases, ensuring functional success of first silicon. A robust post-silicon verification methodology is critical to speeding up time-to-ramp and to prevent loss of product revenue. Formal verification has been deployed as one of the means to root cause silicon failure due to functional error. To ensure correct RTL fix, it is vital to be able to effectively reproduce a failure observed in silicon test and recreate it in RTL environment. One way of getting the RTL failure recreated quickly is by writing the failure scenario in terms of property and using formal tool to generate traces that lead to the failure. In this paper, we describe how simulation, formal and emulation technology coupled with capabilities instrumented in our test generators and RTL for repeatability helped isolate faults, run millions of new verification cycles to validate RTL fixes and formally prove the fixes to be error free. We also share impact of our post-silicon validation strategy on productization schedule of Sun UltraSPARC T2 processor.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"53 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126005023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Automatic generation of functional coverage models from CTL 从 CTL 自动生成功能覆盖模型

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI: 10.1109/HLDVT.2007.4392806

Shireesh Verma, I. Harris, Kiran Ramineni

引用次数: 10

Challenges in post-silicon verification of IBM’s Cell/B.E. and other game processors IBM Cell/B.E.后硅验证的挑战以及其他游戏处理器

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI: 10.1109/HLDVT.2007.4392785

Shakti Kapoor

引用次数: 0

Automatic error diagnosis and correction for RTL designs RTL设计的自动错误诊断与校正

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI: 10.1109/HLDVT.2007.4392789

Kai-Hui Chang, I. Wagner, V. Bertacco, I. Markov

引用次数: 49

Circuit design and verication with Esterel v7 and Esterel Studio 使用Esterel v7和Esterel Studio进行电路设计和验证

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI: 10.1109/HLDVT.2007.4392800

G. Berry

引用次数: 7