{"title":"Automatic generation of functional coverage models from CTL","authors":"Shireesh Verma, I. Harris, Kiran Ramineni","doi":"10.1109/HLDVT.2007.4392806","DOIUrl":null,"url":null,"abstract":"Functional coverage models which measure the sufficiency of test stimuli are essential to the verification process. A key source of difficulty in their deployment emanates from the manual and imprecise nature of their development process and the lack of a sound measure of their quality. A functional coverage model can be considered complete only if it accurately reflects the behavior of the Design under Verification (DUV) as described in the specification. We present a method to automatically generate coverage models from a formal CTL description of design properties. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International High Level Design Validation and Test Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HLDVT.2007.4392806","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
Functional coverage models which measure the sufficiency of test stimuli are essential to the verification process. A key source of difficulty in their deployment emanates from the manual and imprecise nature of their development process and the lack of a sound measure of their quality. A functional coverage model can be considered complete only if it accurately reflects the behavior of the Design under Verification (DUV) as described in the specification. We present a method to automatically generate coverage models from a formal CTL description of design properties. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design.