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1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)最新文献

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On synthesis of manufacturable and testable analog integrated circuits 可制造和可测试模拟集成电路的合成
1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) Pub Date : 1998-08-09 DOI: 10.1109/MWSCAS.1998.759501
Wei-Hsing Huang, J.A. Resh, C. Wey
{"title":"On synthesis of manufacturable and testable analog integrated circuits","authors":"Wei-Hsing Huang, J.A. Resh, C. Wey","doi":"10.1109/MWSCAS.1998.759501","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759501","url":null,"abstract":"In order to maximize chip yield, both design centering and tolerance design find the optimal solutions on both nominal parameter values and tolerances. However, the approaches require a tremendous amount of computation time to find an optimal solution. Based on the sensitivity analysis, an alternative process for synthesizing manufacturable and testable analog ICs is presented. The developed process takes the desired manufacturability to define the bounds of acceptability region for the parameter space and then maps the parameter bounds to performance bounds. Based on the given design specifications, i.e., performance bounds, optimal solutions on the parameters are selected. The process guarantees the circuit with the selected parameters and the specified parameter tolerances will satisfy the design specifications with the desired manufacturability. Since the performance bounds are defined in this process, the frequencies that cause higher sensitivities are selected as the test frequencies so that the designed analog circuits can be fully testable.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125240258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Implementation of an application-specific fuzzy controller by means of a mixed-signal sequential architecture 通过混合信号序列结构实现特定应用的模糊控制器
1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) Pub Date : 1998-08-09 DOI: 10.1109/MWSCAS.1998.759523
E. Alaron, M. Iannazzo, J. Madrenas, J. M. Moreno, S. Gombriz, F. Guinjoan, A. Poveda
{"title":"Implementation of an application-specific fuzzy controller by means of a mixed-signal sequential architecture","authors":"E. Alaron, M. Iannazzo, J. Madrenas, J. M. Moreno, S. Gombriz, F. Guinjoan, A. Poveda","doi":"10.1109/MWSCAS.1998.759523","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759523","url":null,"abstract":"A mixed-signal VLSI circuit that efficiently maps the processing required for a fuzzy knowledge-based controller (FKBC) is presented. The proposed architecture is constituted by digitally programmable continuous-time blocks to perform inference and switched-current memory cells to store in current-mode the partial information resulting from its pipeline operation. This FKBC is intended to provide multidimensional nonlinear function approximation for switching power converter optimum control. Details of a new pulse-width-modulated defuzzyfication scheme are included. Transistor level post-layout simulation results for a 0.8 /spl mu/m CMOS technology are included which validate the different block operations, their compatibility and the feasibility of the sequential architecture.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133350335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Super-resolution from image sequences-a review 来自图像序列的超分辨率——综述
1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) Pub Date : 1998-08-09 DOI: 10.1109/MWSCAS.1998.759509
Sean Borman, R. Stevenson
{"title":"Super-resolution from image sequences-a review","authors":"Sean Borman, R. Stevenson","doi":"10.1109/MWSCAS.1998.759509","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759509","url":null,"abstract":"Growing interest in super-resolution (SR) restoration of video sequences and the closed related problem of construction of SR still images from image sequences has led to the emergence of several competing methodologies. We review the state of the art of SR techniques using a taxonomy of existing techniques. We critique these methods and identified areas which promise performance improvements.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124137146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 414
Self-consistent analysis of nuclear gamma resonance and its industrial applications 核磁共振自洽分析及其工业应用
1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) Pub Date : 1998-08-09 DOI: 10.1109/MWSCAS.1998.759497
P. A. D. de Souza, O. Rodrigues, M. M. Lamego, V. Garg
{"title":"Self-consistent analysis of nuclear gamma resonance and its industrial applications","authors":"P. A. D. de Souza, O. Rodrigues, M. M. Lamego, V. Garg","doi":"10.1109/MWSCAS.1998.759497","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759497","url":null,"abstract":"The present paper reviews the main progress in automation of Mossbauer spectroscopy data analysis by using genetic algorithms, fuzzy logic, and artificial neural networks. Tests were carried out and the results of several applications are presented and discussed.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124143083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Network properties of a pair of generalized polynomials 一类广义多项式的网络性质
1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) Pub Date : 1998-08-09 DOI: 10.1109/MWSCAS.1998.759447
M. Swamy
{"title":"Network properties of a pair of generalized polynomials","authors":"M. Swamy","doi":"10.1109/MWSCAS.1998.759447","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759447","url":null,"abstract":"In this article, it is shown that there exists an intimate relationship between the network functions of certain ladder one-port and two-port networks, and a set of generalized two-variable polynomials defined by U/sub n/(x,y)=xU/sub n-1/(x,y)+yU/sub n-2/(x,y), n/spl ges/2, U/sub 0/(x,y)=0, U/sub 1/(x,y)=1, and V/sub n/(x,y)=xV/sub n-1/(x,y)+yV/sub n-2/(x,y), n/spl ges/2, V/sub 0/(x,y)=2, V/sub 1/(x,y)=x. Observing that well-known polynomials such as Fibonacci, Chebyshev, Jacobsthal, Pell and Morgan-Voyce polynomials are special cases of these generalized polynomials, it is shown how using these polynomials we can derive elegant relations amongst these various polynomials. Also, using the well-established properties of two-element-kind one-and two-port networks, we then obtain a number of interesting results regarding the location of the zeros of these polynomials, as well as their derivatives.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117031024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High efficiency multiplexing scheme for multi-channel A/D conversion 多路A/D转换的高效复用方案
1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) Pub Date : 1998-08-09 DOI: 10.1109/MWSCAS.1998.759548
D. Petrinović
{"title":"High efficiency multiplexing scheme for multi-channel A/D conversion","authors":"D. Petrinović","doi":"10.1109/MWSCAS.1998.759548","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759548","url":null,"abstract":"Multiplexing technique is frequently used in multichannel analog to digital (A/D) conversion, thus reducing the system complexity and cost. However, if the sampling frequencies of the input channels are not equal, obtaining high A/D converter utilization is rather complicated. A new rule-based synchronous multiplexing scheme for multi-channel A/D conversion with different channel sampling frequencies is proposed. It is optimal in the sense that the required A/D conversion frequency is a minimum. The channel sequencing is based on the earliest deadline principle, similar to the one used in real-time dynamic scheduling algorithms.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"775 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116413944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
An adaptive virtual re-partitioning-based windowing technique for motion compensation 一种基于自适应虚拟重分割的运动补偿加窗技术
1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) Pub Date : 1998-08-09 DOI: 10.1109/MWSCAS.1998.759423
Jingyi Zhang, M. Ahmad, M. Swamy
{"title":"An adaptive virtual re-partitioning-based windowing technique for motion compensation","authors":"Jingyi Zhang, M. Ahmad, M. Swamy","doi":"10.1109/MWSCAS.1998.759423","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759423","url":null,"abstract":"The authors describe a new windowing technique for frames partitioned region-wise or using variable-size blocks, where the virtual repartitioning operation for a given region is carried out adaptively and performed locally. Compared to the existing methods, this technique utilizes more pixels that are in the close neighborhood of the boundaries of the regions in the windowing operation, resulting in a substantial reduction in the prediction error as well as in the blocking effect.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127262680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated digital CMOS time-to-digital converter with 92 ps LSB 一个集成的数字CMOS时间-数字转换器与92 ps LSB
1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) Pub Date : 1998-08-09 DOI: 10.1109/MWSCAS.1998.759464
A. Mantyniemi, T. Rahkonen, J. Kostamovaara
{"title":"An integrated digital CMOS time-to-digital converter with 92 ps LSB","authors":"A. Mantyniemi, T. Rahkonen, J. Kostamovaara","doi":"10.1109/MWSCAS.1998.759464","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759464","url":null,"abstract":"An integrated digital CMOS time-to-digital converter with 92 ps LSB width and 50 ps single shot resolution has been designed. The measurement is based on a counter and a novel two step parallel interpolation that uses only 32 delay elements to provide 128 LSBs in the interpolator. The current consumption of the circuit is <20 mA from a single +5 V supply.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126242293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a 3.3 V 12 bit CMOS D/A converter with a high linearity 3.3 V 12位高线性CMOS D/ a转换器的设计
1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) Pub Date : 1998-08-09 DOI: 10.1109/MWSCAS.1998.759549
K. Ryu, K. Yoon, H.K. Min
{"title":"Design of a 3.3 V 12 bit CMOS D/A converter with a high linearity","authors":"K. Ryu, K. Yoon, H.K. Min","doi":"10.1109/MWSCAS.1998.759549","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759549","url":null,"abstract":"This paper describes a 3.3 V, 65 MHz 12 bit CMOS current-mode DAC designed with a 8 MSB current matrix stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with a ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch has been employed. The simulation results of the designed DAC show a conversion rate of 65 MHz, a power dissipation of 71.7 mW, a DNL of /spl plusmn/0.2 LSB and an INL of /spl plusmn/0.8 LSB with a single power supply of 3.3 V for a 0.6 /spl mu/m n-well CMOS technology.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121285030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Median biased Steiner tree heuristics in the rectilinear plane for low-power physical layout 低功耗物理布局的直线平面中值偏置Steiner树启发式方法
1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) Pub Date : 1998-08-09 DOI: 10.1109/MWSCAS.1998.759484
M. Jiménez, M. Shanblatt
{"title":"Median biased Steiner tree heuristics in the rectilinear plane for low-power physical layout","authors":"M. Jiménez, M. Shanblatt","doi":"10.1109/MWSCAS.1998.759484","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759484","url":null,"abstract":"Two heuristics are proposed for the rectilinear Steiner-minimum tree (SMT) problem arising when interconnecting multiple terminals in a layout with obstacles. Efficient algorithms are implemented to convert circuit layouts into graphs. A set of reduction techniques are implemented to remove unfeasible vertices. These techniques delete an average of over 90% of the m Steiner candidates in O(m/sup 2/) time. The proposed SMT heuristics grow trees biased by the terminal distances of the n vertices in a graph in O(n/sup 2/.log n) time. The results obtained highlight their suitability to be used as wire length estimators in a power optimizing placement tool.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114227310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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